1. Modeling and Design for Large Scale Heterogeneous Integration Neil Goldsman Dept. of Electrical and Computer Engineering, UMCP Collaborators: B. Jacob, A. Akturk, Z. Dilli, T. Chitnis, M. Khbeis and G. Metze

2. Modeling and Design for Large Scale Heterogeneous Integration Major Goal: Design, model and fabricate high performance circuits and systems using optimized devices, circuits, as well as 3D and wafer-level integration.

3. Outline Conventional Multi-Chip PC Board Integration  Summary and Limitations Solutions Research Tasks for Achieving Solutions  Device and Mixed Mode Modeling  Interconnect Modeling  Circuit Prototyping  Interconnect Prototyping and Characterization  Passive components achievable with 3D fabrication Summary for Achieving High Performance 3D Integrated System

4. Processor

5. Integrated Systems Systems using a mixed-signal multi-chip PCB architecture: –Communication circuits –High performance computers –Information capture and processing InputOutput

6. Limiting Factors in Multi-Chip PCB Integration Contact Pads Internal and External Interconnects Chip Package Pins Printed Circuit Board Lines and Connections Between Active Circuits Individual Device and Inverter Switching Speeds and Current Drive

7. Problems with Conventional Multi-Chip Integration Bond Pad Bond Wire Transmission Line Pins Transmission Line InputOutput IC 1IC 2 Chip-to-chip PCB integration is limiting: The parasitics of the bond pads, wires and board buses limit speed, driving capability and functionality

8. Problems with Conventional Multi-Chip Integration Increased demand for complexity…

9. Problems with Conventional Multi-Chip Integration …does NOT improve matters

10. Limitations in Integration In fact, not only interconnects but each level in the integration hierarchy imposes its own limitations on the system performance. Speed Power Parasitics Speed Power Noise Speed Power Parasitics (C & L) Crosstalk

11. Search for Solutions to Integration Bottlenecks Focus on improved device design for devices with higher driving capability on pads and interconnects Focus on improved circuit design and layout to minimize the parasitic effect of pads and interconnects 3-D integration (3-DI) Wafer-scale integration (WSI)

12. Wafer Level & 3D Solutions To nullify some of the negative effects of chip-to- chip interconnects Wafer-Scale Integration (WSI)Three-Dimensional Integration

13. Research Tasks 1.Model and design devices optimized for speed and drive 2.Develop mixed signal modeling algorithms to design fundamental circuit elements for drive and speed. 3.Develop algorithms and codes for modeling interconnect parasitics (C and L) 4.Design and prototype circuits for implementation in 3D and wafer level integration. 5.Design and fabricate 3D and wafer level interconnect test structures and passive circuit elements. 6.Measure to extract parasitics for characterization of 3D interconnects. 7.Combine Tasks 1 through 6 to design and fabricate high performance 3D circuit.

14. Task1. Model and Design devices optimized for speed and drive

15. Modeling: Device Dimensions and Doping Profiles Optimized for Switching & Drive Dopant Concentrations of the Devices Doping Profile of a 0.1  m Physical Gate Length Source Side Halo Implanted NMOSFET 1.Contact Regions: S/D (0.3  m wide), Gate (0.1  m wide), 2.Spacer (0.1  m wide) 3.Gate Oxide (25Å tall, 0.3  m wide) 4.Highly Doped Source/Drain (0.1  m tall, 0.35  m wide) LDD Regions are at the edges of channel (0.05  m tall, 0.05  m wide) 5.Substrate (0.5  m tall, 0.9  m wide) 6.Halo (0.01  m thick, either around the Source or Drain) DevicesD SUB (cm -3 )D HALO (cm -3 )D LDD (cm -3 )D S/D (cm -3 ) Halo1x10 16 5x10 17 5x10 18 1x10 20 Conventional5x10 17 -5x10 18 1x10 20 Asymmetric Doping

16. Modeled DC Current Densities for Different NMOS Structures Asymmetric Best DD Equations Supplementary DD Equations Coupled Discretized DD Equations are solved at each mesh point DC Current Densities of NMOS for |V GS |=(0.4,0.7,1.0)V and V SB =0V

17. Electric Fields in Channel Explain Improvement of Asymmetrical Device (a) Lateral and (b) Vertical Surface Electric Fields of NMOS at V GS = V DS =1V

18. Modeled NMOS Turn-on Characteristics (a) Turn-on and (b) Turn-off Characteristics of NMOS

19. Task2. Develop mixed signal modeling algorithms to design fundamental circuit elements for drive and speed.

20. DD Equations Supplementary DD Equations Coupled Discretized DD Equations are solved at each mesh point CMOS Inverter (CMI) Lumped KCL equation check at the output node and using the KCL equation, the output guess is updated for the next iteration, V O i+1 : Mixed-Mode Simulator

21. Modeled Transfer Characteristics of CMOS Inverters Transfer Characteristics of CMOS Inverters with(out) a Resistive Load. Output Current Densities of CMOS Inverters

22. Switching Characteristics of CMOS Inverters without a Capacitive Load.

23. Switching Characteristics of CMOS Inverters with Capacitive Loads Switching Characteristics of CMOS Inverters with C L =0.3pF/20  m. Switching Characteristics of CMOS Inverters with C L =10fF/20  m.

24. Net Charge Density During Low-to-High Input Transition The variation of the net charge density at the conventional MOSFET during low-to-high transition. NMOS and PMOS channels are around 0-0.1 and 1.0-1.1 μms along the lateral x, respectively.

25. Task 3: Calculation of the Induced Voltage on Floating Metals via Capacitive Effects

26. A Typical Bus allows one Write and certain number of Reads through a single line while the remaining connections are kept in high Impedance or floating states.

27. Voltages induced on the floating pins due to the capacitive network

28. Simulation We developed a simulation tool to find the induced voltages on the floating metals due to the pins tied up to a fixed voltage source in an arbitrary rectangular geometry. Net Charge is zero inside the metals and the insulator that is filling the region between the metals Total charge concentration on the floating metals is zero The potential is constant for the fixed metals

29. 2D Simulation Result Here, there are 36 metals uniformly distributed on our mesh grid. The voltages on the two metals at the opposite corners are set to 0 and 10V, and the rest is left to float. Potential Distribution

30. 3D Simulation Result The previous distribution is kept for 3 layers in the z direction (3 rd -5 th ), and no other metals are put outside this z range Potential Distribution at z=4 Isopotential Surfaces

31. Capacitances In Multiconductor Systems The relation between potential and charge is linear By LU decomposition, we find the voltages on the floating metals, (V F1 -V FL ), using the C matrix and the voltages of the fixed metals, (V M1 -V MM ). Then, we find the potential distribution by the utilization of the Conjugate Gradient Method.

32. w=3um t Typical Inductance of Internal Interconnect

33. Proposed Model: Coupling Maxwell Eqns. to Semiconductor Transport Eqns.: Assuming isothermal condition: T= constant. Collisional time, u n : electron mobility Nonlinearity: collisional term (mobility) is a nonlinear function. Keeping inertial term in the momentum equation to account for the electron finite response time.

34. Task 4: Design and prototype circuits for implementation in 3D and wafer level integration.

35. Prototype Processor Verilog HDL Teaching ISA TI ‘C6000 DSP ISA in progress Fully pipelined Handles interrupts precisely Can boot an RTOS (or OS …) INSTRUCTION MEMORY DATA MEMORY REGISTER FILE Program Counter TGT SRC1 SRC2 SRC1SRC2 CONTROL PC Update MUX TGT WDATAADDR RDATA ADDR ALU Result Bus ALU INSTRUCTION OPCODE

36. Phase-Locked Loops Can be designed and operated both for analog and digital signals

37. FM Transceiver The quintessential analog communication system representative Transmitter Receiver

38. Task 5: Design and fabricate 3D and wafer level interconnect test structures and passive circuit elements. On-Chip Inductors and Transformers: Surface versus 3D

39. Current Sheet Approach Valid for geometries with small spacing between between the metal lines. Approximates a square Spiral with four trapezoids forming a square. Adjacent trapezoids don’t have mutual inductance since current flow in them is perpendicular.

40. Different Inductor Geometries Square Inductor Hexagonal Inductor Octagonal Inductor

41. Square Transformer – One Inductor Outside Another Advantages : -High Self Inductance -Low terminal to substrate capacitance -Low terminal to terminal capacitance Disadvantages : -Low Mutual coupling (0.3 – 0.5) Parameters : Li = 2.3 nH ( Inner L) Lo = 3.56 nH ( Outer L) LT = 9.87 nH ( Total L) M = 2.00 nH ( Mutual L) K = 0.35 ( Coupling ) Area = 350 um 2

42. Reducing Parasitic Capacitance of Surface Inductor SiO 2 supports Air Gap formed by etching Removing the Silicon Dioxide reduces the capacitance to substrate and is expected to improve Inductor Quality Factor. Layout 3-D Picture (not to scale) (Connection to pads not shown)

43. Layout3-D Picture ( not to scale) (connection to Pads not shown) Wafer 2 Wafer 1 Air Gap(formed by etched out Silicon Dioxide) Vertical Vias 3D Allows Much Larger L Area of Via = 2  m x 2  m Dimension of Layout : W = 250  m, L = 450  m Number of turns = 100 ; Inductance = 115 nH

44. Comparison of Areas and Inductances AreaInductance Square Spirals32400  m 2 2.5 nH 48000  m 2 8.1 nH Hexagonal Spirals32500  m 2 2.3 nH 48000  m 2 7.6 nH Octagonal Spirals35000  m 2 3.5 nH 55000  m 2 11.7 nH 3-D Inductors 28800  m 2 28.8 nH (Expected Inductance)57600  m 2 57.74 nH 115200  m 2 115 nH

45. Task 6: Measure to extract parasitics for characterization of 3D interconnects. Preliminary analysis indicates pad, pin parasitics are significantly detrimental. Test structure layout complete; submission to Northrop Grumman immenant. (M. Khbeis, G. Metze)

46. Conclusion Conventional Multi-Chip PC Board Integration  Summary and Limitations Solutions Research Tasks for Achieving Solutions  Device and Mixed Mode Modeling  Interconnect Modeling  Circuit Prototyping  Interconnect Prototyping and Characterization  Passive components achievable with 3D fabrication

47. Bond Pad Electro-Static Discharge (ESD) Die (Integrated Circuits) An IC with Bonding Pads

48. Chip-to-Chip Connection on PC Board: Bond Pad Bond Wire Transmission Line Pins InputOutput Die (Integrated Circuits) PC Board Standard Planar Technology Implementation: IC Chips on PCBs

49. Bond Pad Bond Wire Transmission Line Pins InputOutput ICs Signal Path in Planar Chip-to-chip Connection

50. Si Substrate Metal Insulator Oxide Metal Layer Substrate Plate Capacitor Pad Parasitic Capacitance vs. Process (Best Case assuming top metal, no ESD) Pad Capacitance

51. Example Circuit: Ring Oscillator Faster! Slower! Bond Pad Digital Circuit Speed Bond Pad Circuit Driving Capacity NMOS: PMOS: Input Capacitance of A CMOS Inverter: Driving a bond pad is equal to driving TEN inverters! Conventional Bonding: Limitations on System Performance

52. IC Package Parasitics Bond Pad Bond Wire Pin Bond Pad (Several Hundred femto-Farad) Bond Wire & Pin (Several nano- Henry) Requires impedance matching in design to: Maximize Power Transformation Eliminate Signal Reflection Minimize Clock Skew Transmission Line IC 1IC 2 Input Output Tune to Z 0 Z0Z0

53. Effect of Pad and Package Parasitics on Circuit Operation Speed Test circuit: Binary-to-Gray-to-Binary converter Objective: To find out max. clock frequency for which Input = Output

54. Effect of Pad and Package Parasitics on Circuit Operation Speed: Simulation Results Device Size ( L = 0.25u) Separate Chips As a stackWithout pads and pins W = 0.5uSpeed80 MHz100 MHz2.5316 GHz Power0.98 mW0.435 mW2.31 mW W = 1.0u Speed133 MHz166 MHz2.5974 GHz Power1.825 mW1.06 mW4.5 mW W = 1.5u Speed200 MHz250 MHz2.6316 GHz Power2.825 mW1.757 mW6.575 mW W = 2.0uSpeed222 MHz333 MHz2.6666 GHz Power3.425 mW2.675 mW8.5 mW

55. Research into Mixed-Signal Architectures Circuit-level research aims to identify bottlenecks and limitations more precisely Design, simulate and fabricate mixed-signal circuits for the purpose –FM transceiver –PLL –Microprocessors –Image sensor systems

56. Processor? Insert material from Dr. Jacob here?

57. Signal networks within the ICs themselves also require investigation Example: Clock and power networks in CPUs Clock networks: H-networks. Power networks: Grids. Reminiscent of some antenna configurations: EM-interference problems? Fan-out and bus-driving problems: Tie-in to new device and circuit architectures Intra-chip interconnect problems

58. Current Sheet Approach (contd..) We require expressions for Self Inductance of a Trapezoidal sheet and mutual inductance between two parallel trapezoidal sheets. Self Inductance of a Trapezoidal sheet and mutual inductance between two parallel trapezoidal sheets is calculated as an extension of the mutual inductance between two unequal sized parallel lines. A further extension of this yields expressions for the inductance of a Square Spiral. This can be extended to Hexagons and Octagons. For example in a Hexagon the adjacent trapezoids have a component of mutual inductance.

59. Current Sheet Approach (contd..) A general expression for the inductance is Where  = Magnetic Permeability n = No. of turns d avg = Average length of element c= Constants depending on the shape of the inductor  = Fill Factor = (nw + (n-1)s)/l w= Width of conductor s= Spacing between conductors l= Average length of element ( Different from d avg for shapes other than square)