2. Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS, Ohio University March 12, 1998

3. Content: n How to build the BDD for a certain function; n Properties of BDD; n Manipulation of BDD; n Application of BDD to the Pass-Transistor design.

4. Build a BDD for F: F=abc+b’d+c’d F a bc+b’d+c’db’d+c’d T E F=aF a +a’F a’

5. Build a BDD for F: F=abc+b’d+c’d F a T E bb c+c’ddc’dd TETE F=a(bF ab +b’F ab’ ) +a’(bF a’b +b’F a’b’ ) F=aF a +a’F a’

6. Build a BDD for F: F=abc+b’d+c’d F a TE bb 10 TETE F=a(bF ab +b’F ab’ ) +a’(bF a’b +b’F a’b’ ) F=aF a +a’F a’... c d c E EE T TT Order: a<b<c<d

7. Re-ordered-BDD (optimal): F=abc+b’d+c’d F a T b 10 T E E c d TT E E Order: b<c<a<d

8. Properties of BDD: n The Reduced Ordered BDD (ROBDD) is a canonical form; n The size of the BDD (the number of nodes is exponential in the number of variables in the worst case; however, BDDs are well-behaved for many functions that are not amenable to two- level representations (e.g., XOR);

9. Properties of BDD: n The logical AND and OR of BDDs have the same complexity. Complementation is inexpensive; n Tautology can be solved in constant time. Indeed, F is a tautology if and only if its BDD consists of the terminal node 1;

10. Properties of BDD: n Covering problems can be solved in time linear in the size of the BDD representing the constrains;

11. On the other hand: n BDD sizes depend on the ordering. Finding a good ordering is not always simple; n There are functions for which the SOP of POS representations are more compact than BDD;

12. On the other hand: n In some cases SOP/POS forms are closer to the final implementation of a circuit. For instance, if we want to implement a PLA.

13. Manipulation of BDD: a a a 10 TE a T E a’ 10

14. Manipulation of BDD: a a a 10 TE a T ab 10 b E E T

15. Manipulation of BDD: a a a 10 TE a a+b 10 b E E T T

16. Manipulation of BDD: a a a 10 TE a abab 10 b E E TT b E T

17. Minimization of BDD: n Identification of isomorphic sub-graphs; n Removal of redundant nodes.

18. Minimization of BDD: F a T b 10 T E E c d T T E E c ddd a 10 101010 T T T E EET T F=abc+b’d+c’d E E

19. Minimization of BDD: F a T b 10 E E c d TE c d a 10 10 T T T E ET T F=abc+b’d+c’d TTE dd 1010 E E E

20. Minimization of BDD: F a T b 10 E E c d TE c d a 10 10 T T T E ET F=abc+b’d+c’d TE d 10 ET E

21. Minimization of BDD: F T b cc d T E F=abc+b’d+c’d a 10 E E d TE a 10 10 T T ET TE d 10 ET E

22. Minimization of BDD: F T b c F=abc+b’d+c’d 10 ET a d 10 ET E T E

23. Realization of the BDD by the pass-transistor design: F=abc+b’d+c’d 10 ET a VDD aa’

24. Realization of the BDD by the pass-transistor design: F=abc+b’d+c’d F T b c T 10 ET a E d 10 ET E aa’ VDD dd’ VDD cc’ bb’ F

25. Realization of the BDD by the pass-transistor design: F=abc+b’d+c’d F T b c T 10 ET a E d 10 ET E aa’ VDD dd’ VDD cc’ bb’ F

26. Conclusion n Pass-Transistor logic design has an extremely simple cell library - just one multiplexer; n BDD representation gives pass-transistor design a powerful synthesis tool; n BDD also provides a rule to judge in which situation we should use pass-transistor logic design and in the other case we should use CMOS.