1. University of Tehran 1 Microprocessor System Design Processor Timing

2. University of Tehran 2 Outline Machine cycle Fetch, decode, execute Processor timing Bus cycles Memory / IO read Memory / IO write

3. University of Tehran 3 Where is a program stored? ;assume that initially ;ds = 2000, bx = 0023, ax = 351C ;cs = 1000, ip = 0005 mov[bx], al;8807 hlt;F4

4. University of Tehran 4 How does the  P works? Fetch Increment Program Counter (CS:IP) by 1 Decode Execute

5. University of Tehran 5 CS:IP FETCH

6. University of Tehran 6 1000:0005 FETCH

7. University of Tehran 7 10005 FETCH

8. University of Tehran 8 10005 LOW HIGH FETCH

9. University of Tehran 9 10005 88 LOW HIGH FETCH

10. University of Tehran 10 10005 88 LOW HIGH FETCH

11. University of Tehran 11 INC. PC

12. University of Tehran 12 INC. PC

13. University of Tehran 13 DECODE mov [bx], ?

14. University of Tehran 14 CS:IP FETCH

15. University of Tehran 15 1000:0006 FETCH

16. University of Tehran 16 10006 FETCH

17. University of Tehran 17 10006 LOW HIGH FETCH

18. University of Tehran 18 10006 07 LOW HIGH FETCH

19. University of Tehran 19 10006 07 LOW HIGH FETCH

20. University of Tehran 20 INC. PC

21. University of Tehran 21 INC. PC

22. University of Tehran 22 DECODE mov [bx], al

23. University of Tehran 23 DS:BX EXECUTE mov [bx], al

24. University of Tehran 24 2000:0023 EXECUTE mov [bx], al

25. University of Tehran 25 20023 EXECUTE mov [bx], al

26. University of Tehran 26 20023 1C EXECUTE mov [bx], al

27. University of Tehran 27 20023 1C HIGH LOW EXECUTE mov [bx], al

28. University of Tehran 28 20023 1C HIGH LOW EXECUTE mov [bx], al

29. University of Tehran 29 CS:IP FETCH

30. University of Tehran 30 1000:0007 FETCH

31. University of Tehran 31 10007 FETCH

32. University of Tehran 32 10007 LOW HIGH FETCH

33. University of Tehran 33 10007 F4 LOW HIGH FETCH

34. University of Tehran 34 10007 F4 LOW HIGH FETCH

35. University of Tehran 35 10007 F4 LOW HIGH INC. PC

36. University of Tehran 36 10007 F4 LOW HIGH INC. PC

37. University of Tehran 37 10007 F4 LOW HIGH DECODE hlt

38. University of Tehran 38 EXECUTE hlt

39. University of Tehran 39 Machine Cycle

40. University of Tehran 40 Machine Cycle Timing Diagram

41. University of Tehran 41

42. University of Tehran 42 Processor Timing

43. University of Tehran 43 Processor Timing Diagram for the 1st fetch machine cycle (M1) of instruction mov [bx],al

44. University of Tehran 44 Processor Timing Diagram for the 2nd fetch machine cycle (M2) of instruction mov [bx],al

45. University of Tehran 45 Processor Timing Diagram for the execute machine cycle (M3) of instruction mov [bx], al

46. University of Tehran 46 Processor Timing Diagram for the 1st fetch machine cycle (M1) of instruction hlt

47. University of Tehran 47 Processor Timing Diagram for any memory read machine cycle

48. University of Tehran 48 Processor Timing Diagram for any memory write machine cycle

49. University of Tehran 49 Processor Timing Diagram for any I/O read machine cycle

50. University of Tehran 50 Processor Timing Diagram for any I/O write machine cycle