3. Random Access Memory (RAM) Technology
Why do computer designers need to know about RAM technology?
Processor performance is usually limited by memory bandwidth
As IC densities increase, lots of memory will fit on processor chip
Tailor on-chip memory to specific needs
Instruction cache
Data cache
Write buffer
What makes RAM different from a bunch of flip-flops?
Density: RAM is much denser
By now, you are probably wondering: Gee, I want to be a computer designer, why do I have to worry about RAM technology?
Well, the reason you need to know about RAM is that most modern computers’ performance is limited by memory bandwidth.
So if you know how to make the most out of the RAM technology available, you will end up designing a faster computer.
Also, if you are going to design a microprocessor, you will be able to put a lot of memory on your chip so you need to know the RAM technology in order to tailor the on-chip memory for your specific needs.
So the bottom line is that better you know about the RAM technology, better a computer designer you will become.
What makes RAM different from a bunch of flip flops?
The main difference is density. For the same area, you can have much more bits of RAM than you can have flip flops.
+2 = 26 min. (Y:06)

4. Memory Speed Unit one billionth of a second ( nanosecond)
DRAM: ns
SRAM: 10-50ns
ROM: ns

5. Timing Diagram Conventions
Input Signal Output Signal
Must be steady Will be steady high or low
high or low
High-to-low Will be changing from
changes permitted high-to-low during
designated interval
Low-to high Will be changing from
changes permitted low-to-high during
designated interval
Don't-Care State changing
(Does not apply) Centerline represents high impedance (off) state

6. The time it takes for new data to be ready to appear at the output
RAM Timing WE CS
Address
Data Out
Valid Address
Access Time
Simplified Read Timing
Access Time
The time it takes for new data to be ready to appear at the output
Input Data
Valid Address
Data In
Address WE CS
Memory Cycle Time
Simplified Write Timing

7. The Clock Cycle The most important parameter
of the clock is the duration of a cycle,
tCYC.

8. Valid Address The old address is removed in clock state S0 and the
address bus floated

9. Address Bus In state S1 a new address becomes Initially, in state
valid for the remainder
of the memory access
Initially, in state
S0 the address
bus contains the
old address

10. Valid Address
tCLAV
We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted
When AS* is active-low it indicates that the address is valid
We now look at the timing of the clock, the address, and the address strobe

11. AS* goes active low after
the address has become valid
AS* goes inactive
high before the address
changes

12. AS* goes low in clock
state S2

13. The data strobe, is asserted at the same time as AS* in a read cycle
The timing of DS* in a read cycle is the same as the address strobe, AS*
The data strobe, is asserted
at the same time as AS*
in a read cycle

14. Data from the memory
appears near the end of
the read cycle

15. The earliest time at which the memory can
begin to access data is measured from the point
at which the address is first valid

16. Data from the memory is latched into
the by the falling edge of the
clock in state S6.

17. Data must be valid
tDICL seconds before
the falling edge of S6

18. We know that the time between the
address valid and data valid is tacc

19. The address becomes
valid tCLAV seconds after
the falling edge of S0

20. From the falling
edge of S0 to the
falling edge of S6:
the address becomes valid
the data is accessed
the data is captured

21. 3 tcyc = tCLAV + tacc + tDICL