1. Weak SRAM Cell Fault Model and a DFT Technique Mohammad Sharifkhani, with special thanks to Andrei Pavlov University of Waterloo

2. 2 Outline Background and motivation  SRAM issues: noise, SNM, weak cells SRAM SNM sensitivity analysis  vs. process variation  vs. non-catastrophic defect resistance  vs. operating conditions Programmable weak SRAM cell fault model DFT for weak cell detection  Detection concept  Implementation Conclusions

3. 3 Static  Process offsets and mismatches  Operating conditions variations Dynamic  Cross-talk  Ripples in power rails   -particles Most of dynamic sources are quasi-static Noise Sources

4. 4 What is SNM? Seevinck et al, JSSC’87 SNM = max static noise, which can be tolerated by an SRAM cell without changing its logical state

5. 5 What is a weak SRAM cell? Let’s consider a standard 6T SRAM cell:

6. 6 What is a weak SRAM cell? Weak cell = a cell with inadequate SNM that can be easily flipped

7. 7 Why Test Weak SRAM Cells? Because weak SRAM cells: Prone to stability faults Manifest reliability problems Can signify defects, which… Escape regular march tests

8. 8 What Does SNM Depend On? Process variation (mismatch / offset):  V TH spread  L EFF, W EFF spread Resistance of non-catastrophic defects:  R BREAK  R BRIDGE Operation conditions:  V BL  V DD  V WL T0CT0C

9. 9 Static Noise Margin as a Function of Process Variation all results for 0.13um technology, read-accessed cell, i.e. V WL =V BL =V DD

10. 10 SNM vs. V TH (Single Transistor) Typical process corner SNM=100% @ zero V TH deviation Driver  strongest impact, load  weakest impact

11. 11 SNM vs. V TH (Single Transistor) Typical + slow process corners For slow: SNM>100% @ zero V TH deviation

12. 12 SNM vs. V TH (Single Transistor) Typical + slow + fast process corners For fast: SNM<100% @ zero V TH deviation

13. 13 SNM vs. V TH (Multiple Transistors) Typical process corner One V TH changes, while some other are biased Strong SNM decline for some V TH combinations (at max asymmetry)

14. 14 SNM vs. L eff and W eff (Single Transistor) SNM=100% for typical geometry Geometry variations – weak impact on SNM (max 7%)

15. 15 Static Noise Margin as a Function of Non-Catastrophic Defect Resistance

16. 16 SNM vs. Break Resistance  R break   SNM SNM vs. gate breaks  weak dependence SNM vs. driver breaks  strong dependence

17. 17 SNM vs. Bridge Resistance  R bridge   SNM SNM vs. R bridge  uniform dependence

18. 18 Static Noise Margin as a Function of Operation Conditions

19. 19 SNM vs. Bit Line Voltage Typical process If V BL >0.8V  SNM=100% If V BL <0.35V  SNM=0% - hard failure (  normal write) If 0.35V 0.8V  SNM linearly 

20. 20 SNM vs. Bit Line Voltage Typical + slow process corners V BL >0.8V  SNM>100% V BL <0.35V  SNM=0% - hard failure (or normal write) 0.35V 0.8V  SNM linearly 

21. 21 SNM vs. Bit Line Voltage Typical + slow + fast process corners V BL >0.8V  SNM<100% V BL <0.35V  SNM=0% - hard failure (or normal write) 0.35V 0.8V  SNM linearly 

22. 22 SNM vs. Global V DD Typical + slow + fast process corners (extreme cases) SNM linearly 

23. 23 SNM vs. Local V DD Local  resistive break in local V DD Typical + slow + fast process corners (extreme cases) @V DD_LOCAL <0.8V SNM=0 @V DD_LOCAL >0.8V SNM linearly 

24. 24 SNM vs. Word Line Voltage Typical process Read-accessed SRAM cell (SNM deviation @V WL =V DD  0%) @V WL <V TH_ACCESS SNM=max @V WL >V TH_ACCESS SNM linearly 

25. 25 SNM vs. Word Line Voltage Typical + slow process corners

26. 26 SNM vs. Word Line Voltage Typical + slow + fast process corners

27. 27 SNM vs. Temperature Weak dependence 10% max (fast ) 2.5% min (slow)

28. 28 Proposed Weak Cell Fault Model and a Programmable DFT Technique

29. 29 Weak cell fault model SNM vs. node- node R @R node-node  [50k ,500k  ] – linear dependence

30. 30 Weak cell fault model Resistor between nodes A and B Which is equivalent to Negative feedback for inverters of an SRAM cell

31. 31 Programmable detection concept

32. 32 Programmable detection concept @ V TEST : weak cell flips good cell does not flip

33. 33 Proposed DFT concept Changing of ratio R brings nodes to different potentials Weak cell will flip and will be detected Good cell will retain data

34. 34 Proposed DFT Algorithm 1.Write background ratio of zeroes and ones 2.Normal precharge 3.Enable n word lines 4.Right after that short bit lines 5.Release word lines 6.Release bit lines

35. 35 Proposed DFT Implementation 1.Write background ratio of zeroes and ones 2.Normal precharge 3.Enable n word lines 4.Right after that short bit lines 5.Release word lines 6.Release bit lines

36. 36 Proposed DFT Simulation Results R weak =200k  (~65% SNM) Five “0”, three ”1” Weak cell is detected!

37. 37 Proposed DFT Simulation Results R weak =200k  (~65% SNM) Three “0”, five ”1” Weak cell is not detected

38. 38 Proposed DFT detection capability R weak =100k  - 500k  Five “0”, three ”1” Weak cell flips for R weak <200k 

39. 39 Conclusions Weak SRAM cells can escape march tests  need DFT Cell stability is sensitive to process and operation disturbances Weak cell fault model is essential in developing test techniques Proposed DFT efficiently detects weak SRAM cells, i.e. cells with inadequate SNM