1. Lecture 3 – MSP430 ISA The Instruction Set Reading: Chapter 5: Architecture of the MSP430 Processor

2. 2 Topics to Cover… MSP430 ISA Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Disassembly Emulated Instructions Lecture 03 - MSP430 ISA

3. MSP430 Architecture3 Lecture 2 Objectives (cont’d) Upon completion this lecture, students will be able to: Covert a MSP430’s assembly instruction into machine code. 3 Instruction Format: I, II, III 27 Core Instructions and 24 Emulated Instructions 7 source addressing modes 4 destination addressing modes

4. MSP430 Architecture4 Lecture 3 Objectives Upon completion this lecture, students will be able to: Disassemble a sequence of MSP430’s machine code into assembly language: Using the opcode to find the corresponding instruction mnemonic. Append “.b” or “.w” using the b/w bit when appropriate. If double operand instruction, decode and list source operand. If single or double operand instruction, decode and list destination operand. If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC. List that address.

5. 5 Problem  Machine More concrete, machine-dependent; error prone, harder to write, read, debug, maintain Abstract, machine-independent; easier to write, read, debug, maintain Assembler 415E 0001 410F 532F 5F0E 4EE1 0000 415E 0001 531E 410F 532F 5F0E 415D 0001 410F 532F 5F0D 4EED 0000 415F 0001 531F 410E 532E 5F0E 41EE 0000 Machine language instructions Instruction = Many cycles Levels of Transformation Compiler MOV.B 0x0001(SP),R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B @R14,0x0000(SP) MOV.B 0x0001(SP),R14 INC.W R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B 0x0001(SP),R13 MOV.W SP,R15 INCD.W R15 ADD.W R15,R13 MOV.B @R14,0x0000(R13) MOV.B 0x0001(SP),R15 INC.W R15 MOV.W SP,R14 INCD.W R14 ADD.W R15,R14 MOV.B @SP,0x0000(R14) Assembly language instructions One statement = Many instructions Coder lampDoesntWork() { if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); } High-level language statements One algorithm = Many statements Algorithm Problem solved by Algorithm Engineer Problem Lecture 03 - MSP430 ISA

6. 6 Instruction Set Architecture The computer ISA defines all of the programmer-visible components and operations of the computer Memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? Register set (Register File) how many? what size? how are they used? Instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). MSP430 ISA Lecture 03 - MSP430 ISA

7. 7 MSP430 ISA RISC/CISC machine 27 orthogonal instructions 8 jump instructions 7 single operand instructions 12 double operand instructions 7 addressing modes. 8/16-bit instruction addressing formats. Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals MSP430 ISA Lecture 03 - MSP430 ISA

8. 8 MSP430 Registers R0 (PC) – Program Counter This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero. After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction. R1 (SP) – Stack Pointer The MSP430 CPU stores the return address of routines or interrupts on the stack User programs store local data on the stack The SP can be incremented or decremented automatically with each stack access The stack “grows down” thru RAM and thus SP must be initialized with a valid RAM address SP always points to an even address, so its LSB is always zero MSP430 ISA Lecture 03 - MSP430 ISA

9. 9 MSP430 Registers R2 (SR/CG1) – Status Register The status of the MSP430 CPU is contained in register R2 Only accessable through register addressing mode - all other addressing modes are reserved to support the constants generator MSP430 ISA Carry bitC Zero bitZ Negative bitN General interrupt enableGIE Turns off the CPU.CPUOFF Oscillator offOSCOFF Turns off the DCO dc generator.SCG0 Turns off the SMCLK.SCG1 Overflow bitV R3 (CG2) – Constant Generator R4-R15 – General Purpose registers RegisterAsConstantRemarks R2 00 - Register mode R2 01 (0) Absolute mode R21000004h+4, bit processing R2 11 00008h +8, bit processing R3 00 00000h 0, word processing R30100001h+1 R31000002h+2, bit processing R3110FFFFh -1, word processing Lecture 03 - MSP430 ISA

10. 10 16 bit Arithmetic Logic Unit (ALU). Performs instruction arithmetic and logical operations Instruction execution affects the state of the following flags: Zero (Z) Carry (C) Overflow (V) Negative (N) The MCLK (Master) clock signal drives the CPU. MSP430 ALU MSP430 ISA Lecture 03 - MSP430 ISA

11. 11 MSP430 Memory Organization MSP430 ISA Lecture 03 - MSP430 ISA

12. 12 MSP430 Instructions There are three formats used to encode instructions for processing by the CPU core Double operand Single operand Jumps The instructions for double and single operands, depend on the suffix used, (.w ) word or (.b ) byte These suffixes allow word or byte data access If the suffix is ignored, the instruction processes word data by default Instruction Formats Lecture 03 - MSP430 ISA

13. 13 MSP430 Instructions Instruction Formats Op-codeInstructionFormat 0000Undefined Single Operand 0001RCC, SWPB, RRA, SXT, PUSH, CALL, RETI 0010JNE, JEQ, JNC, JC Jumps 0011JN, JGE, JL, JMP 0100MOV Double Operand 0101ADD 0110ADDC 0111SUBC 1000SUB 1001CMP 1010DADD 1011BIT 1100BIC 1101BIS 1110XOR 1111AND 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 4 to 16 Decoder Op-code 1514131211109876543210 0100010100000100 Instruction Register Memory 0100010100000100 mov.w r5,r4 0001000000000101 rrc.w r5 0010111111100100 jc main 0100000000110001 mov.w #0x0600,r1 0000011000000000 PC Lecture 03 - MSP430 ISA

14. 14 MPS430 Instruction Formats Format I: Instructions with two operands: 1514131211109876543210 Op-codeS-regAdb/wAsD-reg MSP430 Instructions 1514131211109876543210 Op-codeb/wAdD/S-reg 1514131211109876543210 Op-codeCondition10-bit, 2’s complement PC offset Format II: Instruction with one operand: Format III: Jump instructions: Lecture 03 - MSP430 ISA

15. 15 Format I: Double Operand Double operand instructions (12 instructions): MnemonicOperationDescription Arithmetic instructions ADD(.B or.W) src,dst src+dst  dst Add source to destination ADDC(.B or.W) src,dst src+dst+C  dst Add source and carry to destination DADD(.B or.W) src,dst src+dst+C  dst (dec) Decimal add source and carry to destination SUB(.B or.W) src,dst dst+.not.src+1  dst Subtract source from destination SUBC(.B or.W) src,dst dst+.not.src+C  dst Subtract source and not carry from destination Logical and register control instructions AND(.B or.W) src,dst src.and.dst  dst AND source with destination BIC(.B or.W) src,dst.not.src.and.dst  dst Clear bits in destination BIS(.B or.W) src,dst src.or.dst  dst Set bits in destination BIT(.B or.W) src,dst src.and.dstTest bits in destination XOR(.B or.W) src,dst src.xor.dst  dst XOR source with destination Data instructions CMP(.B or.W) src,dst dst-srcCompare source to destination MOV(.B or.W) src,dst src  dst Move source to destination Double Operand Instructions Lecture 03 - MSP430 ISA

16. 16 Example: Double Operand Copy the contents of a register to another register Assembly:mov.w r5,r4 Instruction code:0x4504 One word instruction The instruction instructs the CPU to copy the 16-bit 2’s complement number in register r5 to register r4 Op-code mov S-reg r5 Ad Register b/w 16-bits As Register D-reg r4 0 1 0 00 1 000 0 1 0 0 Double Operand Instructions Lecture 03 - MSP430 ISA

17. 17 Format II: Single Operand Single operand instructions: MnemonicOperationDescription Logical and register control instructions RRA(.B or.W) dst MSB  MSB  … LSB  C Roll destination right RRC(.B or.W) dst C  MSB  …LSB  C Roll destination right through carry SWPB( or.W) dst Swap bytesSwap bytes in destination SXT dst bit 7  bit 8…bit 15 Sign extend destination PUSH(.B or.W) src SP-2  SP, src  @SP Push source on stack Program flow control instructions CALL(.B or.W) dst SP-2  SP, PC+2  @SP dst  PC Subroutine call to destination RETI @SP+  SR, @SP+  SP Return from interrupt Single Operand Instructions Lecture 03 - MSP430 ISA

18. 18 Example: Single Operand Logically shift the contents of register r5 to the right through the status register carry Assembly:rrc.w r5 Instruction code:0x1005 One word instruction The CPU shifts the 16-bit register r5 one bit to the right (divide by 2) – the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register Op-code rrc b/w 16-bits Ad Register D-reg r5 0 0 0 1 0 0 0 0 000 0 1 Single Operand Instructions Lecture 03 - MSP430 ISA

19. 19 Jump Instruction Format Jump instructions are used to direct program flow to another part of the program. The condition on which a jump occurs depends on the Condition field consisting of 3 bits: 000: jump if not equal 001: jump if equal 010: jump if carry flag equal to zero 011: jump if carry flag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N  V) 111: unconditional jump Jump Instructions 1514131211109876543210 Op-codeCondition10-bit, 2’s complement PC offset Lecture 03 - MSP430 ISA

20. 20 Jump Instruction Format Jump instructions are executed based on the current PC and the status register Conditional jumps are controlled by the status bits Status bits are not changed by a jump instruction The jump off-set is represented by the 10-bit, 2’s complement value: Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction Note: Use a BR emulated instruction to jump to any address Jump Instructions Lecture 03 - MSP430 ISA

21. 21 Example: Jump Format Continue execution at the label main if the carry bit is set Assembly:jc main Instruction code:0x2fe4 One word instruction The CPU will add to the incremented PC (R0) the value -28 x 2 if the carry is set Op-code JC Condition Carry Set 10-Bit, 2’s complement PC offset -28 0 0 10 1 11 1 1 1 1 0 0 1 0 0 Jump Instructions Lecture 03 - MSP430 ISA

22. MSP430 Addressing Modes the ways in which operands can be specified.

23. 23 Source Addressing Modes The MSP430 has four modes for the source address: 00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+ Addressing Modes Lecture 03 - MSP430 ISA

24. 24 Destination Addressing Modes There are two modes for the destination address: 0 = Rd - Register 1 = x(Rd) - Indexed Register In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) Addressing Modes Lecture 03 - MSP430 ISA

25. 25 00 = Register Mode Addressing Modes Registers ALU CPU Memory ADDER add.w r4,r10 ;r10 = r4 + r10 PC R10 R4 IR Data Bus (+1 cycle) 0x540a Address Bus PC Lecture 03 - MSP430 ISA

26. Memory 26 01 = Indexed Mode Addressing Modes Registers ALU Address Bus Data Bus (+1 cycle) CPU ADDER add.w 6(r4),r10 ;r10 = M(r4+6) + r10 0x0006 PC R10 R4 IR Data Bus (+1 cycle) 0x541a Address Bus PC Lecture 03 - MSP430 ISA

27. Memory 27 10 = Indirect Register Mode Addressing Modes Registers ALU Address Bus Data Bus (+1 cycle) CPU ADDER add.w @r4,r10 ;r10 = M(r4) + r10 PC R10 R4 IR Data Bus (+1 cycle) 0x542a Address Bus 0x542a PC Lecture 03 - MSP430 ISA

28. Memory 28 Addressing Modes Registers ALU Data Bus (+1 cycle) CPU ADDER 11 = Indirect Auto-increment Mode add.w @r4+,r10 ;r10 = M(r4+) + r10 PC R10 R4 IR Data Bus (+1 cycle) 0x543a Address Bus PC 0x543a Address Bus 0002 Lecture 03 - MSP430 ISA

29. Memory 29 Addressing Modes Registers ALU Address Bus Data Bus (+1 cycle) CPU ADDER 01 w/R0 = Symbolic Mode ( PC Relative ) cnt add.w cnt,r10 ;r10 = M(cnt) + r10 0x000c PC R10 IR Data Bus (+1 cycle) 0x501a Address Bus 0x501a PC Lecture 03 - MSP430 ISA

30. Memory 30 Addressing Modes Registers ALU Address Bus Data Bus (+1 cycle) CPU ADDER cnt 01 w/R2 = Absolute Mode 0000 add.w &cnt,r10 ;r10 = M(cnt) + r10 0xc018 PC R10 IR Data Bus (+1 cycle) 0x521a Address Bus 0x521a PC Lecture 03 - MSP430 ISA

31. Memory 31 Addressing Modes Registers ALU CPU ADDER 11 w/R0 = Immediate Mode add.w #100,r10 ;r10 = #100 + r10 PC R10 Data Bus (+1 cycle) IR Data Bus (+1 cycle) 0x503a Address Bus PC 0x503a 0x0064 Lecture 03 - MSP430 ISA

32. Memory 32 Addressing Modes Registers ALU CPU ADDER Constant Generator add.w #1,r10 ;r10 = #1 + r10 PC R10 0000 0001 0002 0004 0008 ffff IR Data Bus (+1 cycle) 0x531a Address Bus PC 0x531a Lecture 03 - MSP430 ISA

33. Memory 33 Addressing Modes Registers ALU Address Bus Data Bus (+1 cycle) CPU ADDER 3 Word Instruction (6 cycles) cnt add.w cnt,var ;M(var) = M(cnt) + M(var) 0x000c PC var Address Bus Data Bus (+1 cycle) PC Data Bus (+1 cycle) 0x0219 IR Data Bus (+1 cycle) 0x501a Address Bus 0x501a PC Lecture 03 - MSP430 ISA

34. 34 Addressing Mode Examples Source Destination Example Rnx(Rn)Sym&abs@Rn@Rn+#nRnx(Rn)Sym&absLen Operation mov r10,r11  1 r10  r11 mov 2(r5),6(r6)  3 M(2+r5)  M(6+r6) mov EDE,TONI  3 M(EDE)  M(TONI) mov &MEM,&TCDAT  3 M(MEM)  M(TCDAT) mov @r10,r11  1 M(r10)  r11 mov @r10+,tab(r6)  2 M(r10)  M(tab+r6), r10+2  r10 mov #45,TONI  3 #45  M(TONI) mov #2,&MEMC  2 #2  M(MEM) mov #1,r11C  1 #1  r11 mov #45,r11  2 #45  r11 Instruction Length Lecture 03 - MSP430 ISA

35. Instruction Length The number of words required to represent the instruction in machine code.

36. 36 Quiz What is the length (in words) for each of the following instructions? InstructionL L add.w r5,r6mov.w EDE,TONI add.w cnt(r5),r6mov.b &MEM,&TCDAT add.w @r5,r6mov.w @r10,r11 add.w @r5+,r6mov.b @r10+,tab(r6) add.w cnt,r6mov.w #45,TONI add.w &cnt,r6mov.w #2,&MEM add.w #100,r6mov.b #1,r11 mov.w r10,r11mov.w #45,r11 mov.w @r5,6(r6)mov.b #-1,-1(r15) mov.w 0(r5),6(r6)mov.w @r10+,r10 Instruction Length 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Lecture 03 - MSP430 ISA

37. 37 Cycles Per Instruction (CPI) Instruction timing: 1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode 1 st to fetch base address 2 nd to fetch source Includes absolute and symbolic modes +2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory Jump instructions are always 2 cycles Lecture 03 - MSP430 ISA

38. 38 Cycles Per Instruction... Instruction Clock Cycles Jump instructions are always 2 cycles. Lecture 03 - MSP430 ISA

39. 39 Example Cycles Per Instruction... ExampleSrcDstCyclesLength add R5,R8RnRm 1 1 add @R5,R6@RnRm 2 1 mov @R5+,R0@Rn+PC 3 1 add R5,4(R6)Rnx(Rm) 4 2 add R8,EDERnEDE 4 2 add R5,&EDERn&EDE 4 2 add #100,TAB(R8)#nx(Rm) 5 3 add &TONI,&EDE&TONI&EDE 6 3 add #1,&EDE#1&EDE 4 2 Instruction Clock Cycles Lecture 03 - MSP430 ISA

40. 40 Quiz How many cycles for each instruction? ;******************************************************************************* ; ;******************************************************************************* ; cycles = --- ; MCLK = --- cycles / 10 seconds = --- Mhz ; CPI = MCLK / --- ; MIPS = MCLK / CPI / 1000000 = --- MIPS.cdecls C,LIST, "msp430.h" ; MSP430 COUNT.equ 0 ; delay count ;------------------------------------------------------------------------------.text ; beginning of executable code ;------------------------------------------------------------------------------ RESET: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT bis.b #0x01,&P1DIR ; set P1.0 as output mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #COUNT,r15 ; use R15 as delay counter delayloop: dec.w r15 ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led ;------------------------------------------------------------------------------ ; Interrupt Vectors ;------------------------------------------------------------------------------.sect ".reset" ; MSP430 RESET Vector.word RESET ; start address.end Lecture 03 - MSP430 ISA

41. Disassembling Instructions Convert machine codes into Assembly language instructions

42. 42 How to Disassembly MSP430 Code 1.Begin with a “PC” pointing to the first word in program memory. 2.Retrieve instruction word and increment PC by 2. 3.Find and list the corresponding instruction mnemonic using the opcode. 4.Append “.b” or “.w” using the b/w bit when appropriate. 5.If double operand instruction, decode and list source operand. 6.If single or double operand instruction, decode and list destination operand. 7.If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC. List that address. Instruction Disassembly Lecture 03 - MSP430 ISA

43. 43 How to Disassemble MSP430 Code 1.Begin with a “PC” pointing to the first word in program memory. 2.Retrieve instruction word and increment PC by 2. Instruction Disassembly R0  0xf800: 4031 0300 mov.w 0xf804: 40b2 5a80 0120 mov.w 0xf80a: d0f2 000f 0022 bis.b 0xf810: 430e mov.w 0xf812: 43a0 09ec mov.w 0xf816: 4ec2 0021 mov.b 0xf81a: 531e add.w 0xf81c: f03e 000f and.w 0xf820: 120e push.w 0xf822: 403e 0200 mov.w 0xf826: 122e push.w 0xf828: 8391 0000 sub.w 0xf82c: 23fd jne 0xf82e: 411e 0002 mov.w 0xf832: 5011 0004 add.w 0xf836: 3fef jmp Lecture 03 - MSP430 ISA

44. 44 How to Disassemble MSP430 Code 3.Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits). 4.Append “.b” or “.w” using the b/w bit when appropriate Instruction Disassembly 0xf800: 4031 0300 mov.w 0xf804: 40b2 5a80 0120 mov.w 0xf80a: d0f2 000f 0022 bis.b 0xf810: 430e mov.w 0xf812: 43a0 09ec mov.w 0xf816: 4ec2 0021 mov.b 0xf81a: 531e add.w 0xf81c: f03e 000f and.w 0xf820: 120e push.w 0xf822: 403e 0200 mov.w 0xf826: 122e push.w 0xf828: 8391 0000 sub.w 0xf82c: 23fd jne 0xf82e: 411e 0002 mov.w 0xf832: 5011 0004 add.w 0xf836: 3fef jmp Lecture 03 - MSP430 ISA

45. 45 How to Disassemble MSP430 Code 5.If double operand instruction, decode and list source operand. Instruction Disassembly 0xf800: 4031 0300 mov.w #0x0300 0xf804: 40b2 5a80 0120 mov.w #0x5a80 0xf80a: d0f2 000f 0022 bis.b #0x000f 0xf810: 430e mov.w #0 0xf812: 43a0 09ec mov.w #2 0xf816: 4ec2 0021 mov.b r14 0xf81a: 531e add.w #1 0xf81c: f03e 000f and.w #0x000f 0xf820: 120e push.w 0xf822: 403e 0200 mov.w #0x0200 0xf826: 122e push.w 0xf828: 8391 0000 sub.w #1 0xf82c: 23fd jne 0xf82e: 411e 0002 mov.w 0x0002(r1) 0xf832: 5011 0004 add.w 0x0004(r0) 0xf836: 3fef jmp Lecture 03 - MSP430 ISA

46. 46 How to Disassemble MSP430 Code 6.If single or double operand instruction, decode and list destination operand. Instruction Disassembly 0xf800: 4031 0300 mov.w #0x0300,sp 0xf804: 40b2 5a80 0120 mov.w #0x5a80,&0x0120 0xf80a: d0f2 000f 0022 bis.b #0x000f,&0x0022 0xf810: 430e mov.w #0,r14 0xf812: 43a0 09ec mov.w #2,0x09ec(r0) 0xf816: 4ec2 0021 mov.b r14,&0x0021 0xf81a: 531e add.w #1,r14 0xf81c: f03e 000f and.w #0x000f,r14 0xf820: 120e push r14 0xf822: 403e 0200 mov.w #0x0200,r14 0xf826: 122e push @r14 0xf828: 8391 0000 sub.w #1,0x0000(r1) 0xf82c: 23fd jne 0xf82e: 411e 0002 mov.w 0x0002(r1),r14 0xf832: 5011 0004 add.w 0x0004(r0),r1 0xf836: 3fef jmp Lecture 03 - MSP430 ISA

47. 47 How to Disassemble MSP430 Code 7.If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC. List that address. Instruction Disassembly 0xf800: 4031 0300 mov.w #0x0300,sp 0xf804: 40b2 5a80 0120 mov.w #0x5a80,&0x0120 0xf80a: d0f2 000f 0022 bis.b #0x000f,&0x0022 0xf810: 430e mov.w #0,r14 0xf812: 43a0 09ec mov.w #2,0x09ec(r0) 0xf816: 4ec2 0021 mov.b r14,&0x0021 0xf81a: 531e add.w #1,r14 0xf81c: f03e 000f and.w #0x000f,r14 0xf820: 120e push r14 0xf822: 403e 0200 mov.w #0x0200,r14 0xf826: 122e push @r14 0xf828: 8391 0000 sub.w #1,0x0000(r1) 0xf82c: 23fd jne $-0x0006 0xf82e: 411e 0002 mov.w 0x0002(r1),r14 0xf832: 5011 0004 add.w 0x0004(r0),r1 0xf836: 3fef jmp $-0x0026 Lecture 03 - MSP430 ISA

48. 48 How to Decode an Operand 1.To decode a source operand: a.Decode the addressing mode from the “As” bits (00=register, 01=indexed, 10=indirect, or 11=indirect auto-increment) and source register from the “S-Reg” bits. b.If “@R2”, “@R2+”, “R3”, “x(R3)”, “@R3”, or “@R3+”, list appropriate constant preceded by pound sign (ie #1). c.Else if “x(R0)”, change to symbolic mode, retrieve index (next code word), add index word to PC, increment PC, and list that address as operand (0x8023). d.Else if “x(R2)”, change to absolute mode, retrieve address (next code word), increment PC, and list address preceded by an ampersand symbol (ie. &addr). e.Else if “@PC+”, change to immediate mode, retrieve immediate value (next code word), increment PC, and list immediate value preceded by the pound symbol (ie. #100). f.Else if register mode, list register (ie. Rn). g.Else if indexed mode, retrieve index (next code word), increment PC, and list index followed by the register in parentheses (ie. 0x0200(R4)). h.Else if indirect mode, list the register preceded by an @ symbol (ie. @R4). i.Else indirect auto-increment mode, list the register preceded by an @ symbol and followed by a plus symbol (ie. @R4+). 2.To decode a destination operand, use the “Ad” bit and the destination register bits. Follow the same steps as for the source operand (except there will only be register and indexed modes – no constants, immediate, or indirect modes). Instruction Disassembly Lecture 03 - MSP430 ISA

49. 49 Addressing Modes Instruction Disassembly Address Mode AsAs AdAd RegistersSyntaxOperation Register000 R0-R2, R4-R15RnRegister Contents. 000– R3#00 Constant source / bit bucket destination Symbolic011 R0ADDR(PC+next word) points to operand. (X(PC)) Indexed011 R1, R4-R15X(Rn)(Rn+X) points to operand. X is next code word. Absolute011 R2&ADDRNext code word is the absolute address. (X(SR)) +101– R3#1+1 Constant Indirect10– R0-R1,R4-R15@RnRn points to operand. +410– R2#4+4 Constant +210– R3#2+2 Constant Immediate11– R0#NNext word is the constant N. (@PC+) Indirect auto-inc11– R1,R4-R15@Rn+Rn points to operand, Rn is incremented (1 or 2). +811– R2#8+8 Constant 11– R3#-1-1 Constant Lecture 03 - MSP430 ISA

50. 50 Quiz Disassemble the following MSP430 instructions: AddressData 0x8010:4031 0x8012:0600 0x8014:40B2 0x8016:5A1E 0x8018:0120 0x801a:430E 0x801c:535E 0x801e:F07E 0x8020:000F 0x8022:1230 0x8024:000E 0x8026:8391 0x8028:0000 0x802a:23FD 0x802c:413F 0x802e:3FF6 Quiz Lecture 03 - MSP430 ISA

51. Emulated Instructions AKA Pseudo-Instructions

52. 52 Emulated Instructions In addition to the 27 instructions defined by the MSP 430 ISA, there are 24 additional emulated instructions. The emulated instructions make reading and writing code more easy, but do not have their own op-codes. Emulated instructions are replaced automatically with native MSP 430 instructions by assembler. There are no penalties for using emulated instructions. Emulated Instructions Lecture 03 - MSP430 ISA

53. 53 Emulated Instructions MnemonicOperationEmulationDescription Arithmetic instructions ADC(.B or.W) dst dst+C  dst ADDC(.B or.W) #0,dstAdd carry to destination DADC(.B or.W) dst dst+C  dst (decimally) DADD(.B or.W) #0,dstDecimal add carry to destination DEC(.B or.W) dst dst-1  dst SUB(.B or.W) #1,dstDecrement destination DECD(.B or.W) dst dst-2  dst SUB(.B or.W) #2,dstDecrement destination twice INC(.B or.W) dst dst+1  dst ADD(.B or.W) #1,dstIncrement destination INCD(.B or.W) dst dst+2  dst ADD(.B or.W) #2,dstIncrement destination twice SBC(.B or.W) dst dst+0FFFFh+C  dst dst+0FFh  dst SUBC(.B or.W) #0,dstSubtract source and borrow /.NOT. carry from dest. Emulated Instructions Lecture 03 - MSP430 ISA

54. 54 Emulated Instructions MnemonicOperationEmulationDescription Logical and register control instructions INV(.B or.W) dst.NOT.dst  dst XOR(.B or.W) #0(FF)FFh,dst Invert bits in destination RLA(.B or.W) dst C  MSB  MSB-1 LSB+1  LSB  0 ADD(.B or.W) dst,dstRotate left arithmetically RLC(.B or.W) dst C  MSB  MSB-1 LSB+1  LSB  C ADDC(.B or.W) dst,dstRotate left through carry Program flow control BR dst dst  PC MOV dst,PCBranch to destination DINT 0  GIE BIC #8,SRDisable (general) interrupts EINT 1  GIE BIS #8,SREnable (general) interrupts NOPNoneMOV #0,R3No operation RET @SP  PC SP+2  SP MOV @SP+,PCReturn from subroutine Emulated Instructions Lecture 03 - MSP430 ISA

55. 55 Emulated Instructions MnemonicOperationEmulationDescription Data instructions CLR(.B or.W) dst 0  dst MOV(.B or.W) #0,dstClear destination CLRC 0C0C BIC #1,SRClear carry flag CLRN 0N0N BIC #4,SRClear negative flag CLRZ 0Z0Z BIC #2,SRClear zero flag POP(.B or.W) dst @SP  temp SP+2  SP temp  dst MOV(.B or.W) @SP+,dst Pop byte/word from stack to destination SETC 1C1C BIS #1,SRSet carry flag SETN 1N1N BIS #4,SRSet negative flag SETZ 1Z1Z BIS #2,SRSet zero flag TST(.B or.W) dstdst + 0FFFFh + 1 dst + 0FFh + 1 CMP(.B or.W) #0,dstTest destination Emulated Instructions Lecture 03 - MSP430 ISA