1. Introduction to MicroElectronics
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Introduction to MicroElectronics
K.El-Ayat, Ch: 1.1 – 1.5 1

2. (a) Thévenin form, (b) the Norton form.
Signal sources
(a) Thévenin form, (b) the Norton form.
Figure 1.1

3. amplitude Va, frequency f = 1/T Hz.
EX: 1 Sine-wave signal
amplitude Va, frequency f = 1/T Hz.
Figure 1.3 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency v = 2pf rad/s.

4. EX 2: A symmetrical square-wave signal of amplitude V.
Figure 1.4 A symmetrical square-wave signal of amplitude V.

5. The frequency spectrum of periodic square wave in EX 2
Useful for signal analysis
Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.

6. Figure 1.2 An arbitrary voltage signal vs(t).

7. Frequency spectrum of arbitrary waveform
Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.

8. Sampling continuous-time analog signal
Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).

9. Binary Digital Signals: variations with time.
Figure 1.8 Variation of a particular binary digital signal with time.

10. Analog-to-digital conversion (ADC) or A/D.
Most signals in real world Analog
Need A/D to process in digital domain
Figure 1.9 Block-diagram representation of the analog-to-digital converter (ADC).

11. NMOS transistor structure
Source (S), Drain (D), Gate (G)
L channel length, W width of transistor
NMOS transistor cross-section
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. 11

12. CMOS structure, today’s ICs
both NMOS & PMOS transistors
PMOS formed in an n-well
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device. 12

13. CMOS Logic gate
Example 1 ?
Figure A two-input CMOS ……. gate.

14. Digital Logic inverter
Figure A logic inverter operating from a dc supply VDD.

15. Inverter Transfer Characteristic VTC = voltage transfer characteristic
Ideal inverter
Typical inverter
Vol = output low; Voh = output high;
Vil = max input interpreted as “0”; Vih = min input interpreted as “1”;
Figure The VTC is approximated by three straight line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

16. Inverter Circuit Implementation
Figure (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when vI is low; and (c) equivalent circuit when vI is high. Note that the switch is assumed to close when vI is high.

17. CMOS inverter implementation The most common inverter
Figure A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10.

18. Inverter Operation
Figure Example 1.6: (a) The inverter circuit after the switch opens (i.e., for t  0). (b) Waveforms of vI and vO. Observe that the switch is assumed to operate instantaneously. vO rises exponentially, starting at VOL and heading toward VOH .

19. Inverter Propagation delays 10/90 rule
Figure Definitions of propagation delays and transition times of the logic inverter.

20. Amplifier: Circuit symbol
Figure (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.

21. Voltage Amplifier & Transfer characteristic
Figure (a) A voltage amplifier fed with a signal vI(t) and connected to a load resistance RL. (b) Transfer characteristic of a linear voltage amplifier with voltage gain Av.

22. Some Amplifiers Require 2 supplies Eg 2 supply +ve & -ve swings
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Some Amplifiers Require 2 supplies
Eg 2 supply +ve & -ve swings
Figure An amplifier that requires two dc supplies (shown as batteries) for operation.

23. Amplifier transfer characteristics
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output
Amplifier transfer characteristics
Amps have limitations .. may saturate ..signal (2)
L+ >= A*vi
Note +ve & -ve swings & amplification see signal 1  output peaks are clipped due to saturation
Amp saturates at L+ when going positive; L- when going negative
Amp linearity desired
Vout(t) = A * Vin(t)
input
Figure An amplifier transfer characteristic that is linear except for output saturation.
How many power supplies ?

24. Amplifier Biasing – ensures linearity
Nonlinear response
Figure (a) An amplifier transfer characteristic that shows considerable nonlinearity. (b) To obtain linear operation the amplifier is biased as shown, and the signal amplitude is kept small. Observe that this amplifier is operated from a single power supply, VDD. 24

25. Inverting Amplifier Example
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Inverting Amplifier Example
Top limit = 10v, lower limit = 0.3v
Output 180 degrees out of phase with input
L+ =~ 10v
@ Vt = 0
Vo = EXP(-11) * eEXP(40Vt)
For 5 V bias
@ Vo = 5v
Vt = 0.673
Need special exponent notation
L- = 0.3v
Vt = 0.690
Figure A sketch of the transfer characteristic of the amplifier of Example 1.2. Note that this amplifier is inverting (i.e., with a gain that is negative).

26. Voltage Amplifier Circuit Model used for simulation, circuit analysis
Gain = Aw; input resistance = Ri, Output resistance = Ro
vo = Aw * vi * RL/(RL + Ro) ; effect of output resistance Ro
vo / vi = Aw * RL/(RL + Ro) ; voltage gain
vi = vs * Ri / (Ri + Rs) ; effect of Ri
vo / vs = Aw * Ri / (Ri + Rs) * RL/(RL + Ro); overall voltage gain accounting for input / output impedances
Figure (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.

27. More Gain ? Use Cascaded stages Ex 1.3
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More Gain ? Use Cascaded stages Ex 1.3
Input stage needs high input impedance
Output stage needs low output impedance
Input resistance of a stage = load resistance of previous stage
Vi1 / Vs = 1 M / ( 1M + 100k) = ; effect of 1st Rin
Av1 = Vi2 / Vi1 = 10 * 100k / (100k + 1k) = ; gain 1st stage, A = 10
Av2 = Vi3 / Vi2 = 100 * 10k / (10k + 1k) = ; gain 2nd stage, A = 100
Av3 = VL / Vi3 = 1 * 100 / ( ) = ; gain 3rd stage, A = 1
Av = VL / Vi1 = 9.9 * 90.9 * = ; 3 stage gain
VL / Vs = 818 * = ; from source to load
Ideal Gain = 10 * 100 = 1000
Figure Three-stage amplifier for Example 1.3.

28. Amplifiers have limited bandwidth  frequency response of Amplifiers
Constant gain between w1 & w2 (Bandwidth) ; otherwise lower gain. Amp chosen so its BW coincides with required spectrum to be amplified … otherwise signals distorted
Figure Typical magnitude response of an amplifier. |T(v)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(v) to the input Vi(v).

29. Frequency Response Amplifier output coupling
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Frequency Response Amplifier output coupling
DC (direct ) coupled
Gain at low freq & DC
Used in IC
a.k.a low-pass amp.
Capacitively coupled
Amp ..Eg audio
Band pass Amp
Bandpass Filter
Tuned Amps.
TV, signal processing..
Capacitors expensive – difficult in IC, DC used
Figure Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.

30. Capacitively Coupled Amplifier Stages
Figure Use of a capacitor to couple amplifier stages.

31. An NMOS Common Source Amplifier
Amp. Circuit
Xfer Characteristic
Figure (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a). 31

32. NMOS common source Amp. Cont’d Xfer Characteristic
Biased at point Q
Figure (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q. 32