1. © 2007 IBM Corporation MICRO-2009 Start-Gap: Low-Overhead Near-Perfect Wear Leveling for Main Memories Moinuddin Qureshi John Karidis, Michele Franceschini Viji Srinivasan, Luis Lastras, Bulent Abali IBM T. J. Watson Research Center, Yorktown Heights, NY

2. © 2007 IBM Corporation 2 Introduction: Lifetime Limited Memories Emerging Memory Technologies (PCM) candidate for main memory. Reasons: Scalability, Leakage Power Savings, Density, etc. Challenge : Each cell can endure 10-100 Million writes  Limited lifetime With uniform write traffic, system lifetime ranges from 4-20 years workloads 16 yrs 4 yrs

3. © 2007 IBM Corporation 3 Problem: Non-Uniformity in Writes Heavy non-uniformity in writes: <10% lines incur 90%+ of write traffic Database workload (writes occur on eviction from a 256MB DRAM cache) Average

4. © 2007 IBM Corporation 4 Expected Lifetime with Non-Uniform Writes 20x lower Even with 64K spare lines, baseline gets 5% lifetime of ideal Num. writes before system failure Num. writes before failure with uniform writes Norm. Endurance = x 100% Baseline w/o spares Baseline (64K spare lines)

5. © 2007 IBM Corporation 5 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

6. © 2007 IBM Corporation 6 Existing Proposals: Table-Based Wear Leveling Wear Leveling: Make writes uniform by remapping frequently written lines. Studied extensively for Flash Memories. Almost all proposals Table based. Line Addr. Lifetime CountPeriod Count A99K (Low)1K (Low) B100K (Med)3K (High) C101K (High)2K (Med)  Line Remap Addr AC BA CB Indirection Table Physical Address PCM Address

7. © 2007 IBM Corporation 7 Disadvantages of Table Based Methods Area overhead can be reduced with more lines per region:  Reduced effectiveness (e.g. Line0 always written)  Support for swapping large memory regions (complex) Overheads: 1. Area of several (tens of) megabytes 2. Indirection latency (table in EDRAM/DRAM) Our Goal: A wear leveling algorithm that avoids the storage, latency, and complexity of table based methods and still achieves lifetime close to ideal.

8. © 2007 IBM Corporation 8 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

9. © 2007 IBM Corporation 9 Start-Gap Wear Leveling Two registers (Start & Gap) + 1 line (GapLine) to support movement. Move GapLine every 100 writes to memory.  START A B C 0 1 2 3 4 PCMAddr = (Start+Addr); (PCMAddr >= Gap) PCMAddr++) D GAP  Storage overhead: less than 8 bytes (GapLine taken from spares) Latency: Two additions (no table lookup) Write overhead: One extra write every 100 writes  1%

10. © 2007 IBM Corporation 10 Results for Start-Gap On average, Start-Gap gets 53% normalized endurance 10X better than baseline, but still 2x lower than Ideal. Why?

11. © 2007 IBM Corporation 11 Spatial Correlation in Heavily Written Regions Start-Gap moves a line to its neighbor  If heavily written regions are spatially close, Start-Gap may move hot lines to other hot lines Peaks Writes Localized If address space is randomized, hot regions will be spread uniformly FFT db1

12. © 2007 IBM Corporation 12 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

13. © 2007 IBM Corporation 13 Randomized Start Gap Line Addr Static Randomizer Start-Gap Mapping Physical Address Randomized Address PCM Address One-to-one mapping  Invertible function. Configured at design/boot. Hot lines PCM Minor change can support Pagemode memory. Randomizer is OS unaware.

14. © 2007 IBM Corporation 14 Efficient Address Space Randomization Two proposals (very little hardware) c0 c1 c2 c3 = b00 b01 b02 b03 b10 b11 b12 b13 b20 b21 b22 b23 b30 b31 b32 b33 RIB Matrix x a0 a1 a2 a3 Random Invertible Binary (RIB) Matrix 85 byte storage (1 cycle latency) Feistel Network (crypto) 5 byte storage (3 cycle latency)

15. © 2007 IBM Corporation 15 Results for Randomized Start-Gap Randomized Start-Gap achieves 97% of ideal lifetime while incurring a total storage overhead of 13 bytes.

16. © 2007 IBM Corporation 16 Analytical Model for Randomized Start Gap Lifetime from analytical model matches very well (97% vs. 96.8%) We developed a simple analytical model that uses variance in write traffic across lines to compute norm. endurance (details in paper)

17. © 2007 IBM Corporation 17 Comparison with Table Based Methods Randomized Start-Gap achieves lifetime similar to hardware-intensive version of table based & avoids several tens of cycle of latency overhead Baseline TBWL-640MB TBWL-1.25MB RandSGap (1 line per region) (region=128KB) 13 bytes Normalized Endurance (%)

18. © 2007 IBM Corporation 18 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

19. © 2007 IBM Corporation 19 Security Challenge in Lifetime Limited Memories What if an adversary knows about write endurance limit? Repeat Address Attack (RAA): repeat writes to same line. RAA can cause line failure in less than 1 minute Time to 1 line failure (seconds) = Endurance * ( CyclesPerWrite / CyclesPerSec ) = 2 25 x 2 12 4GHz = 32 seconds Both baseline and randomized Start-Gap suffers from this attack. Even table based wear leveling (practical version) suffers.

20. © 2007 IBM Corporation 20 Security Aware Wear Leveling Solution: Divide memory into regions. One Start-Gap per region. Region size is made such that each line in region guaranteed to move once every “endurance” number of writes to region NumLinesInRegion < Endurance WritesPerGapMovement We use 256K lines per region (256 regions). Area Overhead < 1.5KB RAA now takes about 3-4 months to cause failure. With delayed writes (in paper), time to failure ranges in year(s)

21. © 2007 IBM Corporation 21 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

22. © 2007 IBM Corporation 22 Summary  Limited endurance poses lifetime and security challenge  Table based wear leveling: area and latency overhead  Start-Gap: Cost-effective wear leveling with two registers  Randomized Start-Gap: 97% of ideal endurance with 13 bytes  We took a first step towards making PCM systems secure against malicious attacks (RAA). Motivation for more research

23. © 2007 IBM Corporation 23 Advertisement HPCA 2010 Tutorial Phase Change Memory: A Systems Perspective Organizers Dr. Moinuddin K Qureshi (IBM Research) Prof. Sudhanva Gurumurthi (University Of Virginia) Dr. Bipin Rajendran (IBM Research) Date: Jan 9, 2010 (Half Day) http://www.cs.virginia.edu/~gurumurthi/PCM_tutorial/

24. © 2007 IBM Corporation 24 Backup Slides

25. © 2007 IBM Corporation 25 Supporting DRAM PageMode with Start-Gap Randomization must be done at a DRAM-Page granularity instead of line

26. © 2007 IBM Corporation 26 Lifetime Under RAA attack RAA will now take about 3-4 months to cause failure. With delayed writes (in paper), time required would range in year(s). 1 week 4 months 1 minute

27. © 2007 IBM Corporation 27 Outline  Problem  Background on Wear Leveling  Start Gap Wear Leveling  Randomized Start-Gap  Security Considerations  Summary

28. © 2007 IBM Corporation 28 Spare Lines