1. Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

2. Noise-subtracting algorithm " Time to frequency transformation " Subtraction of magnitudes " Distortion correction " Frequency to time transformation Algorithm Modules FFT Subtraction In- / Output

3. Noise-subtracting algorithm Algorithm Modules FFT Subtraction In- / Output

4. Noise-subtracting algorithm " Serial data " Shifts of 16bits " Storing in 1032 x 32bit memory " Flushing memory to FFT after receiving of 256 pairs of data Algorithm Modules FFT Subtraction In- / Output

5. Noise-subtracting algorithm State machine storing data in memory Flushing memory Buffering data Emptying buffer Reset256 pairs Mem flushed Buffer emptied Algorithm Modules FFT Subtraction In- / Output

6. Noise-subtracting algorithm Block Diagram Data SCLK LRCLK ResetData Address WR RD Flushing EnableDone Hold Data Real part Imaginary Valid Output Serial shifter 16bit counter Address generator Buffer Finite state machine 1024 x 32bit RAM Algorithm Modules FFT Subtraction In- / Output

7. Noise-subtracting algorithm " Parallel input and output of variables " 16Bit address, 8Bit data (compatible to microcontroller) " Preset values when resetting Algorithm Modules FFT Subtraction In- / Output

8. Noise-subtracting algorithm " Implementation of Radix 2 algorithm " Window length 1024 " 16Bit fixed point arithmetics " 2 FFTs at the same time by using real and imaginary signal " Reconstruction afterwards needed Algorithm Modules FFT Subtraction In- / Output

9. + + WkWk A B C D - x Noise-subtracting algorithm " Butterfly structure as fundamental cell Algorithm Modules FFT Subtraction In- / Output

10. Noise-subtracting algorithm W0W0 W0W0 W2W2 W2W2 W3W3 W0W0 W2W2 W1W1 f(0) f(7) F(0) F(1) F(2) F(3) F(4) F(5) F(6) F(7) Signal-flow Graph for 8 point FFT Algorithm Modules FFT Subtraction In- / Output

11. Noise-subtracting algorithm " Sequential implementation " 1Bit shiftdown after each step to prevent overflow " RAM 1024 x 32Bit " Controller (Finite state machine) " Address generator " Coefficient ROM Algorithm Modules FFT Subtraction In- / Output

12. Noise-subtracting algorithm ram_addr1 Controller Address Generator RAM Butterfly Processor Coeff. ROM rom_addr ram_addr2 twiddle write_en read_en Data Bus io_mode fft_mode input_mode fft_doneio_done bus_select Data In Data Out input_readyoutput_ready 1010 10 32 FFT PROCESSOR Block Diagram Algorithm Modules FFT Subtraction In- / Output

13. Noise-subtracting algorithm Delay estimation Input: 512 FFT processing:2*512*10 output:512 Sum 11264 clock cycles Algorithm Modules FFT Subtraction In- / Output

14. Noise-subtracting algorithm Simulations Algorithm Modules FFT Subtraction In- / Output

15. Noise-subtracting algorithm Spectra reconstruction Re Im Re Im Re Im Algorithm Modules FFT Subtraction In- / Output

16. Noise-subtracting algorithm Error compared to 32bit floating point 020004000600080001000012000 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Absolute Error Algorithm Modules FFT Subtraction In- / Output

17. Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules FFT Subtraction In- / Output

18. (absolute values plotted) Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules FFT Subtraction In- / Output

19. C.O.R.D.I.C An acroynm for: –Coordinate Rotation DIgital Computer

20. CORDIC? WHY USE IT? " CORDIC was derived by Volder in the 50’s to calculate trigonometric function. " CORDIC can also calculate hyperbolic, linear and logarithmic functions. " CORDIC processing offers high computational rates  fast enough for demanding DSP tasks. " Hardware-efficient algorithm, requires only shifts and adds.

21. THE CORDIC ALGORITHM Provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds. Multiplication by tangent term can be avoided if the rotation angles are restricted to tan(  )=2^-i. In digital hardware = simple shift operation. The individual equations can be rewritten rearranged so that: The basic CORDIC-equations for rotation and vectoring mode:

22. Vectoring and Rotation Modes Rotation mode performs Polar to Cartesian transformation by rotating the input vector by a specified angle (given as an argument). Vectoring mode performs Cartesian to Polar transformation by rotating input vector to the x-axis while recording the angle required to make that rotation.

23. Word-Parallel Pipelined CORDIC CORDIC Processor core built around three fundamental modules: –Pre-Processor: manipulates inputs to fit in -1 to +1 rad. so that the algorithm covers entire 2  range. –CORDIC core: performs actual algorithm in parallel using a pipeline of CordicPipe blocks. –Post-Processor: places results in correct quadrant.

24. RECTANGULAR TO POLAR CONVERSION Takes two 16-bit signed words as inputs (Xin,Yin) CORDIC core returns equivalent polar coordinates where Rout is the magnitude and Aout is the angle. Outputs are in fractional format with the upper 16-bits represent decimal value and lower 4-bits represent fractional value.

25. POLAR TO RECTANGULAR CONVERSION Takes 16-bit magnitude from subtraction and stored angle as inputs (Rin, Ain). CORDIC core returns equivalent rectangular coordinates Xo and Yo. Core only converges in the range -90 to +90 degrees, must write a pre and post processor so that algorithm covers entire 2  range.

26. FUTURE WORK " Need to write test bench for rect2polar and polar2rect modules. " Need to finish writing pre and post processor for polar2rect module. " Need to connect my modules to my partners modules. " Need to test and verify that they work well together.

27. Noise-subtracting algorithm 16 Alpha Beta Sub Comp a sel b 1 if x>y, else 0 x Block diagram Algorithm Modules FFT Subtraction In- / Output

28. Noise-subtracting algorithm Inputs: two, 16 unsigned bits each ( A and B) Multiplication: Alpha and Beta terms Subtraction: ((original A)-(Alpha*B)) Comparators: (A > B) out =1, else out =0 Multiplexer: (Inputs: Select, A*Beta, subtractor output) Select = 1, final_out = x Select = 0, final_out = y Algorithm Modules FFT Subtraction In- / Output

29. FUTURE WORK " Connect all modules together. " Need to write and verify RTL code. " Synthesize all code and implement in FPGA. " Test FPGA.