1. High Energy Density Charge Storage Capacitors Martin Peckerar, Neil Goldsman, Zeynep Dilli Department of Electrical and Computer Engineering University of Maryland College Park, MD 20742

2. Where the Capacitor Fits Into the System “ Rectenna ” Storage Capacitor Block Microwave In To System

3. The Basic Capacitor Structure N+ Silicon Metal Hi-k Dielectric a. Cross-section of a corrugated capacitor b. Disposition of the silicon posts in the Corrugated array

4. LAYOUT WITHIN A CHIP a a b b c c a+b=k, a constant c=250 microns An n x n array, where: n=(9500/(a+b))

5. 1 cm 1mm a 11 b 11 a 12 b 12 a 21 b 21 An m x m array, where: m = 8 a ij + b ij =c ij c ij =160microns/(i+j) Plate Layout a ij =(8-i)c ij /8 b ij =ic ij /8 i and j range from 1 to 8

6. GDS2 “Blow-Back”* Chip-In Mask Layout Blow-up of corner square Showing pillar tops *This is a graphic display of the actual data used to prepare the mask

7. In-Chip GDS2 “Blow-Back”

8. Goal of the Experiment The varying aspect ratio of the pillars will allow us to make a curve like the following: capacitance aspect ratio yielding Zero-yield

9. Process Flow start etch dope insulate metal

10. The Final Step: Stacking the Battery Tiles 1cm < 0.01cm