1. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 1 GLAST Large Area Telescope: Electronics, Data Acquisition & Flight Software Electronics Gunther Haller Stanford Linear Accelerator Center Manager, Electronics, DAQ & FSW LAT Chief Electronics Engineer haller@slac.stanford.edu (650) 926-4257 Gamma-ray Large Area Space Telescope

2. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 2 Electronics Outline Overview Team Front-End Electronics Tower Electronics Module –GLAST Calorimeter Cable Controller ASIC (GCCC) –GLAST Tracker Cable Controller ASIC (GTCC) GAS Unit GLAST Global Trigger Controller (GLTC) SIU/EPU Crate –LAT Communication Board –Spacecraft Interface Board –Processor Spacecraft Interface Verification & Test Testbed Summary

3. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 3 LAT Electronics (Signals) TKR: Tracker CAL: Calorimeter ACD: Anti-Coincidence Detector TEM: Tower Electronics Module EPU: Event Processor Unit SIU: Spacecraft Interface Unit GAS Unit: Global Trigger- ACD-Signal Distribution Unit

4. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 4 LAT Electronics (Power) TKR: Tracker CAL: Calorimeter ACD: Anti-Coincidence Detector TEM: Tower Electronics Module EPU: Event Processor Unit SIU: Spacecraft Interface Unit GAS Unit: Global Trigger- ACD-Signal Distribution Unit PDU: Power Distribution Unit* * PDU is presented separate in Power System presentation

5. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 5 Team Manager –Gunther Haller, SLAC Flight Software Lead –JJ Russell, SLAC DAQ System Lead –Mike Huffer, SLAC Mechanical-Thermal Lead –Dave Nelson, SLAC Power-EMI Lead –Dave Nelson, SLAC EGSE Lead –Mike Huffer, SLAC I&T Lead –Dave Nelson, SLAC Mission Assurance Lead –Darren Marsh, Nick Virmani (SLAC, Swales) Manufacturing Lead –Jerry Clinton, SLAC Flight-Software Team: see FSW presentation Front-End Simulator –Mark McDougald, SLAC Parts –Mark Freytag, SLAC Harness –Dave Nelson, Mark Freytag, SLAC Packaging –Jobe Noriel, SLAC ASIC & Board Analysis –Dieter Freytag, Oren Milgrome, SLAC TKR sub-system electronics –Manager: Robert Johnson, UCSC –EE: Dave Nelson, SLAC CAL sub-system electronics –System Manager: Neil Johnson, NRL –EE: Jim Ampe, NRL ACD sub-system electronics –Manager: Dave Thompson, GSFC –EE: Glenn Unger, GSFC Power Distribution Unit –Patrick Young, SLAC GAS Unit –Joszef Ludvig, SLAC TEM DAQ Module –Leonid Sapozhnikov, SLAC Tower Power Supply –Vendor (Oversight: Dave Nelson, SLAC) Spacecraft Interface Board –Michael Lovellette, Greg Clifford, Dennis Silver (NRL & Silver Engineering) –Software: Dan Wood (NRL) Crate Backplane –Robert O’Leary, SLAC Crate Power Supply Board –Robert O’Leary, SLAC LAT Communication Board –Sandra Frazier, SLAC GLAST Tracker Cable Controller ASIC –Leonid Sapozhnikov, Noman Ahmed, SLAC GLAST Calorimeter Cable Controller ASIC –Leonid Sapozhnikov, Noman Ahmed, SLAC GLAST Global Trigger ASIC –Joszef Ludvig, Noman Ahmed, SLAC

6. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 6 Tracker Electronics TKR sub-system electronics Si-Strip Detectors 24 GTFE (GLAST Tracker Front-End) ASIC (1,536 signal channels) 2 GTRC (GLAST Tracker Readout Controller) ASIC MCM (Multi-Chip Module) Flex-cables Presented in tracker sub-system CDR GTFE ASIC GTRC ASIC

7. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 7 Calorimeter Electronics CAL sub-system electronics Diodes 48 GCFE (GLAST Calorimeter Front-End) ASIC 4 GCRC (GLAST Calorimeter Readout Controller) ASIC AFEE (Analog Front-End Electronics) board Presented in calorimeter sub-system CDR GCFE ASIC GCRC ASIC

8. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 8 ACD Electronics ACD sub-system electronics PMT’s 18 GAFE (GLAST ACD Front-End) ASIC 1 GARC (GLAST ACD Readout Controller) ASIC FREE (Front-End Electronics) board High-Voltage Supply board (not shown) Presented in ACD sub-system CDR GAFE ASIC GARC ASIC

9. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 9 Tower Electronics DAQ Module Main DAQ module, one on each tower –Controls and reads out data from TKR MCM and CAL AFEE front-end electronics –Zero-suppresses CAL event data –Buffers events in cable ASIC FIFO’s –Assembles CAL and TKR event fragments to tower event –Transmits data to GASU –Contains monitoring and low-rate science circuits –LVDS interface to front-end electronics and GASU –Hardware with software controlled configuration and mode registers CAL ICD: LAT-SS-00238 TKR ICD: LAT-SS-00176 TEM ICD: LAT-SS-00363 Trigger Controller Control, Event & HSK Signals Power Power from TEM PS Module TKR (8 cables) Trigger TKR Cable ASIC CAL Cable ASIC CAL (4 cables) Common Controller Power to TEM Elex Trigger signals to/from Global Trigger on GAS Unit Control & HSK signals from/to SIU, Event data to EPU, all via GAS Unit

10. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 10 Tower Electronics DAQ Module (Con’t) Engineering Model with full functionality and interfaces as flight has been used extensively in 18 copies in the field, controlled and readout with real-time software from the FSW group, and I&T software from the I&T group Not just tested in TEM test-setup at SLAC, but more importantly fully integrated in set-ups with real sub-system electronics –at NRL and at SLAC with CAL electronics –In Italy and at SLAC with TKR electronics –At SLAC, NRL with DAQ electronics Flight Model with 8 GTCC and 4 GCCC ASIC, plus 2 ACTEL’s: design finished, ready for layout/fabrication LAT-TD-00605

11. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 11 Tower Electronics Module GCCC ASIC GLAST Calorimeter Cable Controller (GCCC) ASIC –TEM interface to calorimeter AFEE Configuration and readback data Trigger and event data handling Log suppression algorithm Event buffers –Contains Two 64x16 FIFO’s Three 128x16 FIFO’s Core Logic LVDS drivers/receivers –VHDL code compiled into XILINX FPGA, is used on TEM’s which are operating with CAL electronics –ASIC in fabrication, expected April 25 –LAT-TD-01549 LVDS IO CORE FIFO GCCC

12. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 12 Tower Electronics Module GTCC ASIC GLAST Tracker Cable Controller (GTCC) ASIC –TEM interface to tracker MCM’s Configuration and readback data Trigger and event data handling Data reformatting Event buffers –Contains Two 64x16 FIFO’s Three 128x16 FIFO’s Core Logic LVDS drivers/receivers –VHDL code compiled into XILINX FPGA, is used on TEM’s which are operating with CAL electronics –ASIC in fabrication, expected April 25 –LAT-TD-01550 LVDS IO CORE FIFO GTCC

13. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 13 Design & Verification for GCCC/GTCC VHDL Simulation Netlist Automatic: Layout, Place&Route Compare Layout: Add IO and LVDS. Result: Complete Chip Layout Automatic: Generate Schematic Manual: Schematic of IO, LVDS Simulation: Spice Full Chip Schematic Netlist Netlist w/o ParasiticsNetlist with Parasitics Full-Chip Simulation with Synopsys Full-Chip Compare/Verific ation Fabrication Test Stress & Timing Analysis Flight-Model Status 3/03

14. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 14 GAS Unit (Signal Distribution and Trigger) Uses GLTC ASIC to receive LVDS signals and to logically mask and combine 228 ACD trigger signals Global Trigger controller –Combines trigger inputs from TKR, CAL, ACD and makes trigger decision –Distributes trigger message with target CPU for event, time- stamp, event-number, and trigger type to sub-systems –Total time from particle in detector to receipt of trigger accept signal: 2  sec Command Response Unit –Distributes control from SIU to TEM’s, GLT, ACD EM, EB –Transmits readback data from TEM’s, GLT, ACD, EB to EPU’s Hardware with software controllable configuration & mode registers –GLT ICD: LAT-TD-01545 –CMD-Response ICD: LAT-SS- 00461; LAT-TD-00606 One prime and one redundant DAQ board

15. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 15 GAS Unit (ACD EM & Event Data) Uses GLTC ASIC to convert LVDS to CMOS signals and to logically mask and combine 228 ACD trigger signals ACD EM –Controls and reads out data from ACD front-end electronics –Buffers events –Assembles 12 ACD event fragments to ACD event –Transmits data to EB –Contains monitoring circuits Event Builder –Receives event fragments from TEM’s, AEM, and GLT at up to 10 KHz rate –Builds LAT event and transmits to EPU’s/SIU’s at up to 10 KHz rate –Receives CPU data, forwards to other CPU’ s or to SC (science data interface) Hardware with software controllable configuration & mode registers –ACD ICD: LAT-SS-00363 –AEM ICD: LAT-TD-00639 –EB ICD: LAT-TD-01546 One prime and one redundant DAQ board

16. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 16 GAS Unit (Con’t) GLAST Global Trigger Controller (GLTC) ASIC –LVDS receivers for ACD veto and CNO trigger signals –Maskable logical-OR function of ACD trigger signal –Handles 18 input signal channels –Contains Core Logic LVDS receivers –First version ASIC was received in Dec 02 –Fully working, is flight design –Flight quantity is on shared LAT wafer-run expected back end of March 03 –LAT-TD-0148 Engineering Model with partial functionality and interfaces as flight has been used in several copies in the field, controlled and readout with real-time software from the FSW group, and I&T software from the I&T group ACD EM at SLAC and GSFC, with real ACD front-end electronics Trigger input signal received and trigger accept message generated via SLAC COM-module (either CAL, TKR, and ACD programmed) Flight Model with 14 GLTC and 9 ACTEL’s: design finished, in layout/fabrication

17. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 17 SIU/EPU Crate Spacecraft Interface Board (SIB) –EEPROM –MIL1553 Communication with spacecraft* –Power Control of PDU/GASU power switches in PDU* –Power Control of VCHP switches in heater box* LAT Communication Board (LCB) –Communication with GASU Commanding Read-back Data Housekeeping Data Event Data Power Supply Board (PSB) –28V to 3.3V/5V conversion –Power-On Reset –LVDS-CMOS conversion of spacecraft discretes* –System clock to GASU CPU Board –Processor –IO of level-converted SC discretes Backplane –passive * Only used in SIU crate

18. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 18 LAT Communication Board

19. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 19 LAT Communication Board (Con’t) PCI-interface engineering model in operation since early 03 (has PMC connector) Flight Model has cPCI connector: design finished, scheduled to be in layout/fabrication 4/03 ICD: LAT-TD-00860

20. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 20 Spacecraft Interface Board Designed/implemented by Silver Engineering (Dennis Silver, Greg Clifford) under contract by NRL –Driver by Dan Wood/NRL Engineering model is in test since mid 02 –6U cPCI PCB Format –Uses J1 of cPCI –12 Layer Polyimide Construction –4 Chassis GND Planes –3 Power and Ground Planes –5 Routing Layers –65 Ohm Controlled Impedance Signals Flight Model adds npn transistors for heater control –Schematic updated –Waiting for layout modification ICD: LAT-SS-01539

21. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 21 Processor BAe750 compact PCI board 750 class Power-PC 240 MIPS at 133 Mhz, Less Than 12W 128 Mbytes main memory 256 Kbytes SUROM Total Dose > 100 kRad (Si), Latchup Immune, SEU Rate < 1E- 5 Upsets/processor-day @ 90% GEO VxWorks real-time operating system –LAT ordered prototype, was received Spring 02 –Since then used for software development at NRL Boot-code Bench-mark for LAT filtering code Test with SIB MIL1553 prototype –Same board selected by GLAST spacecraft contractor To be ordered April 03

22. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 22 LAT Spacecraft Interface Power –28V regulated and unregulated MIL1553 –Commanding Science Interface (LVDS) –Transport of science data to spacecraft solid-state recorder 1-PPS timing signal (LVDS) –Timing pulse GBM GRB Candidate signal (LVDS) –Notification of candidate Gamma-Ray Burst (GRB), from GBM routed through SC Discretes (LVDS) –Pulsed and level digital signals from and to spacecraft Analog Monitoring –Temperature and voltage monitoring by SC without having LAT powered Two power/signal sets: Prime and redundant All agreed to: Spectrum Astro SC-LAT Interface Document LVDS: Low-Voltage-Differential-Swing signaling

23. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 23 Power Interface to Spacecraft All power feeds from spacecraft can be turned off/on via ground Spacecraft turns off SIU/DAQ feeds when going to survival mode LAT start-up ICD: LAT- TD-01536 –Describes process of cold and warm boot (bring-up) of LAT

24. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 24 Spacecraft 1-PPS and GRB Candidate Signal 1-PPS signal from spacecraft prime and redundant are connected to both GASU DAQ boards (prime and redundant) GASU DAQ selects which SC signal to use Result is fanned out to all processor crates (SIU’s as well as EPU’s) Crate DAQ selects which GASU signal to use SC-LAT components are fully cross-connected Same for GBM GRB candidate signal

25. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 25 Spacecraft Discrete Signal Discrete Signals from SC to LAT: –Discrete LVDS-signals from spacecraft prime and redundant are connected to both SIU crates (prime and redundant) –Reset discrete: P and R SC signal is logically Or’ed and used as CPU reset –Spare discretes: CPU selects whether to use P or R input and result is routed to CPU discrete inputs (3 prime and 3 redundant) Discrete Signals from LAT to SC (not shown) –Discrete LVDS-signals from LAT SIU P and SIU R are driven to both, prime and redundant, spacecraft C&DH (Control & Data Handling) systems

26. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 26 LAT-SC Science Interface GASU event builder –Directs data from TEM’s to any of the CPU’s (not shown) –Directs data from CPU to CPU –Directs data from CPU to spacecraft Any CPU can direct data via either GASU DAQ (P or R) to SC Data is driven to both SC sections (P and R) –SC needs to select which GASU to listen to –GASU needs to know from which SC (P or R) the flow-control line is valid –All configured via ground commanding

27. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 27 Harness Almost exclusively point-to-point cables (not harness) Connectors are Micro-D and Sub-D Cables are shielded-twisted pair, 24 AWG Installation in layers; assembly drawings close to complete Designed an fitted on 1:1 LAT model

28. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 28 Example: Connections LAT/Spacecraft and to LAT EMI Shield

29. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 29 Connections LAT/Spacecraft and to LAT EMI Shield (focus)

30. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 30 Verification & Test: Example TEM & FSW Processor: Motorola Power-PC Flight Software PMCIA LAT Communication Board for –LAT Communication Transition Board –Trigger TEM DAQ Assembly TEM Power-Supply Assembly 28-V Supply LAT-TD-00861 Tower Power Supply Assembly (1.5V/2.5V/3.3V/ 0-100V/0-150V) TEM DAQ Assembly LCB: LAT Communication Module Transistion-card: Trigger Module 28-V Power Supply Power-PC Processor Flight Software

31. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 31 Verification & Test: RAD750/SIB 3u-cPCI BAE RAD750 processor prototype 6u-cPCI Spacecraft Interface Board (Silver Engineering) – MIL1553 interface Flight Software –Boot code development –SIB board code driver/interface Courtesy of Dan Wood, NRL SIB CPU

32. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 32 Verification & Test: Front-End Data Simulator System uses 9 PC’s –8 PC’s for 16 TEM’s –1 PC for ACD Data transported to towers via high-speed data link; PCI bridge to local bus on simulator Data Simulators interface to TEM like CAL and TKR sub-system electronics –CAL and TKR simulator board identical except code in FPGA’s –Patch cable connect simulator to CAL and TKR TEM connectors Can operate TEM or LAT with data generated from simulations Data simulator board in layout

33. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 33 Verification & Test: Testbed TEM DAQ Modules TEM Power Supplies TKR and CAL Electronics Simulators 12 ACD Electronics Cards Full DAQ set with EM2 hardware (each with identical interfaces and functionality as flight) Incremental built according to plan (complete testbed Feb04) All DAQ modules including 16 TEM’s Harness like flight TKR and CAL front-end electronics for 1 tower, front-end simulator boards for other 15 towers Full set of ACD EM2 electronics Spectrum Astro SC simulator Excellent hardware and software testbed Spectrum Astro Simulator

34. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 34 Verification & Test: Spacecraft Interface Use Spectro-Astro provided Spacecraft Instrument Interface Simulator (SIIS) Power –Manual off-on switch Control & Data Handling (C&DH) –MIL1553 –Science Interface (LVDS) –1-PPS timing signal (LVDS) –GBM GRB Candidate signal (LVDS) –Discretes (CMOS) –Analog Monitoring Present plan is for SIIS to only provide –Primary interface can’t test prim-redundant interface response –Timing accuracy of 1 PPS interface not sufficient to test timing interface performance Work in progress LVDS: Low-Voltage-Differential-Swing signaling

35. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 35 Summary Flight designs for electronics components well advanced Engineering models in use in EGSE test-stands Flight-designs of DAQ ASIC’s submitted to fabrication Component verification and test plans described To be worked on: –Worst-case & timing analysis plus test-procedures for several modules still need to be completed –EM2 tests (multi-tower with GASU) scheduled to be started end of April 03 –Documents still need to be completed The electronics is ready to purchase flight components/hardware

36. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 36 Backup

37. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 37 Trigger Path TKR, CAL, and ACD produce fast (< 700 ns) trigger input signals from their front-end comparators –CAL, LO and HI discriminator signals LO is used as monitor trigger for TKR HI is used for very high energy (>10GeV) events –TKR, Layer OR –ACD, LO and HI discriminator signals LO is efficient for minimum ionizing particles HI selects CNO events TEM produces sub-system specific trigger primitives for CAL & TKR (e.g. 3-in-a-row) Global Trigger in GASU receives trigger inputs from ACD and TEM’s and decides whether to trigger the instrument If instrument is triggered, Trigger Accept signal is distributed back to front-ends -> Event data is generated Total time from particle in detector to receipt of trigger accept signal: < 2 usec GASU ( includes Global Trigger) Trigger Inputs TEM Trigger Accept TKR CAL ACD 16 Towers

38. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 38 Event Data Path Event data from CAL & TKR are acquired by TEM’s, reformatted, buffered, and transmitted via GASU to all Processor Units (for ACD the TEM function is included in the GASU) EPU’s assemble LAT events and filter the data to reduce the event rate of ~6 KHz down to ~30 Hz Events arriving at EPU’s have target EPU ID in header, so each EPU only processes sub-set of events and forwards filtered events via GASU to other processors or spacecraft solid-state recorder All pipe-line stages subject to flow- control Dead-time is monitored on an event- by-event basis GASU Event Data EPU /SIU TEM Data to Spacecraft TKR CAL ACD Towers

39. GLAST LAT ProjectDOE/NASA Peer Critical Design Review, March 19-20, 2003 G. Haller 4.1.7 Electronics V5 39 Assemble TEM Event Datapath & Building Events Front-End TEM CAL-TRG FIFO CAL ADC Data With 3 Events Digitize on trigger TKR FIFO With 1 Event ~50,000 TKR GTFE MEM Cells With 2 Events Latch on trigger FIFO for each Tower Event Builder Cable Event Processing Unit (EPU) Trigger Data Accept/ Reject From other TEM’s Assemble LAT Event Processor SW Filter Tower Spacecraft