1. PADS Power Aware Distributed Systems Middleware Techniques and Tools USC Information Sciences Institute Brian Schott, Bob Parker UCLA Mani Srivastava Rockwell Science Center Charles Chien

2. PADS Project Q: How can you extend the dynamic power range of sensor networks from quiescent months of monitoring to frenetic minutes of activity? Architectural Approaches  Power Aware Research Platform Testbed  Deployable Power Aware Sensor Platform Middleware, Tools, and Techniques  Power Aware Resource Scheduling in RTOS  Techniques for Network-Wide Power Management Power Aware Algorithms  Multi-Resolution Distributed Algorithms UCLA

3. Introduction to UCLA PADS Team PI  Mani Srivastava Other faculty  Rajesh Gupta Students  Sung Park, Pavan Kumar, Paleologos Spanos, Vijay Raghunathan, Cristiano Ligieri, and Ravindra Jejurikar

4. Research Agenda Broad goals  Middleware techniques for “JIT” power through coordinated scheduling and power management of computing and communication resources locally at a sensor node (RTOS) as well as globally in a sensor network (protocols)  Tools for evaluating and designing the power management techniques  Target 10-30x gain in power efficiency Specific subtasks  Power management within a sensor node Power-aware RTOS scheduling under timing constraints Resource management with energy-speed and energy-accuracy control knobs Tools for RTOS power management evaluation, and power-aware kernel synthesis  Network-wide power management Network resource allocation for global power management Power-aware network protocols Hybrid sensor network simulation framework for power vs. quality evaluation of network level power management techniques and protocols  Power management with multimedia sensor data Power characterization, extension of PADS techniques to streaming multimedia  Integration with sensor nodes (Rockwell nodes, research platform)

5. Accomplishments Since Last Review I. Power measurement, analysis, and modeling  Power models for SensorSim  Power analysis of various nodes in the lab II. Power management of sensor node processor via RTOS  Adaptive power-fidelity trade-off via prediction of run-time  Implementation on eCos  Validation on multimedia and sensor processing tasks  Development of generic API to power-aware OS (on-going)  Tools to evaluate power management strategies (on-going) III. Power management of sensor node radio  Development of the “dynamic modulation scaling” concept  Various energy-aware wireless packet scheduling techniques IV. Power-aware sensor node architecture  Energy-efficient packet forwarding architecture for sensor nodes  Experimental validation via lab prototype V. Publications  One at International Conference on VLSI Design (published)  Three at ISLPED (accepted)  One at Sigmetrics (accepted)  One at Winter Simulation Conference (accepted)  Some more submitted

6. I. Sensor Network Power Measurement, Analysis & Modeling Data from SensIT Experiments DAQ Power Measurements SensorSim Simulator SensorViz Node Locations Target Trajectories Sensor Readings User Trajectories Query Traffic Power Models

7. SensorSim Architecture Target Node Sensor Layer Physical Layer Sensor Stack Sensor Channel Target Application Wireless Channel User Application User Node Network Layer Physical Layer Network Stack MAC Layer Sensor Layer Physical Layer Sensor Stack3 Sensor Layer Physical Layer Sensor Stack2 Functional Model Sensor Node SensorWare Power Model Battery Model Radio CPU ADC (Sensor) Wireless Channel Sensor Channel1 Network Layer MAC Layer Physical Layer Network Stack Sensor Layer Physical Layer Sensor Stack1 Sensor App Sensor Channel2 Sensor Channel3 Sensor Node Wireless Channel Sensor Channel User Node Target Node

8. Power analysis of sensor nodes: Where does the power go? High-end sensor node: Rockwell WINS nodes  StrongARM processor  Connexant’s RDSSS9M 900MHz DECT radio (128 kbps, ~ 100m)  Seismic sensor Low-end sensor node: Experimental node similar to Berkeley’s COTS motes  Atmel AS90LS8535 microcontroller  RF Monolithic’s DR3000 radio (2.4, 19.2, 115 kbps, ~ 10-30m)  No sensors (but microcontroller has ADC)

9. Power Analysis of Rockwell’s WINS Nodes (Measurements) Summary Processor  Active = 360 mW doing repeated transmit/receive  Sleep = 41 mW  Off = 0.9 mW Sensor = 23 mW Processor : Tx = 1 : 2 Processor : Rx = 1 : 1 Total Tx : Rx = 4 : 3 at maximum range  comparable at lower Tx

10. Power Analysis of Experimental Node (Measurements) Note All powers in mW Microcontroller (with ADC) Active = 8.7 mW Idle = 5.9 mW Off = 3  W

11. Some Observations from Power Analysis In WINS node, radio consumes 33 mW in “sleep” vs. “removed”  Argues for module level power shutdown Tx and Rx power  Rx power within 40% of maximum Tx power  Under certain circumstances, Tx power < Rx power!  Argues for: MAC protocols that do not “listen” a lot Low-power paging (wakeup) channel Processor power fairly significant (30-50%) share of overall power Sensor transducer power negligible  Use sensors to provide wakeup signal for processor and radio

12. Understanding Battery Lifetime & Impact of DC-DC Regulator

13. II. Power Management for Wireless Sensor Node Processor SensorsRadio CPU (Minimalist) Real Time Operating System Power Manager Dynamic Voltage Scaling Scalable Signal Processing Dynamic Modulation Scaling Coordinated Power Management

14. Predictive DVS for Adaptive CPU Power-Fidelity Tradeoff Power aware RTOS for embedded applications Wireless systems resilient to packet loss Time varying computational load Proactive DVS strategy involving prediction of task instance runtime Up to 75% reduction in energy over worst case based voltage scheduling with negligible loss in fidelity (up to 4% deadline misses) on variety of multimedia and signal processing tasks Normalized energy Average Exec. Time / Worst Case Exec. Time

15. Implementation Implemented under eCoS using Intel’s Assabett board  DVS-enabled eCoS on iPaQ to be ready soon

16. Power-aware API eCoS Application Threads Power-Management Functions DVS HAL Normal eCoS System Calls Power Related Task Data Structures Hardware Power-aware Task Scheduler To OS: task: set period, set deadline, set WCET, set actual remaining execution time, set hard/soft, create task instance interrupt handler: create task instance To Task Instance: get remaining execution time, kill Why? Ease of porting to different processors Allow apples-to-apples comparison on the same set o f applications

17. Tool to Evaluate Power Management Strategies Current approach: simulation  Simulation framework using PARSEC to compare different power management strategies under various types of task schedulers  Problem: long simulations, biased by choice of specific task set Ongoing: analysis-based tool  Based on “competitive analysis” to derive worst case bounds on improvement yielded by a power management strategy metric: competitive ratio = how much worse than optimal off-line strategy  Take into account transition cost (power, time)  Implementation based on formal model checking tool which is used as a simulator for power management policy  Problems: excessive memory hog, only a bound Future: integrate analysis and simulation

18. III. Dynamic Power Management of Sensor Node Radios SensorsRadio CPU (Minimalist) Real Time Operating System Power Manager Dynamic Voltage Scaling Scalable Signal Processing Dynamic Modulation Scaling Coordinated Power Management

19. T bit (  s) R S (MHz) b E bit (  J) R S (MHz) b Dynamic Modulation Scaling Energy and delay of data transmission depend on modulation settings Tradeoffs for QAM  adapt b (number of bits per symbol)  Operate at maximum R S that can be implemented efficiently Similar tradeoffs are possible for other scalable modulation schemes  PSK, DPSK  ASK  OFDM

20. Analogy Between Dynamic Voltage and Modulation Scaling Scaling modulation on the fly results in energy awareness Strong analogy between modulation scaling and voltage scaling  Low power techniques, like parallelism  Packet scheduling like task scheduling  Other power management techniques E bit (  J) T bit (  s) b = 6 b = 4 b = 2 Vb f RbRb Voltage scaling Modulation scaling

21. Analogy Between Dynamic Voltage and Modulation Scaling Radio Digital Hardware

22. T av (  s) E av (  J) Queue-Based Dynamic Modulation Scaling Radio Dynamic Power Management (R-DPM) for best-effort data packet service Adapt modulation based on number of packets in the queue Radio Queue Processor R-DPM Different {queue, b}-settings result in different points on the energy-delay tradeoff

23. Energy Aware Real Time Packet Scheduling Analogous to RTOS task scheduling Exploit variation in packet length to perform aggressive DMS Up to 69% reduction in transmission energy Framework for coordinated power management of computing and communication sub-systems L avg /L max Energy savings (%)  static  dyn  stretch  static  dyn  static

24. Data Combining versus Modulation Scaling Data combining  Gains depend on correlation in time or space  Reduction in packet size or increase in reliability Modulation scaling Overall tradeoff e scaling (  J/packet.hop) t scaling (  s/packet.hop) Modulation scaling tradeoff e comb t comb Data combining tradeoff Combining

25. IV. Power-aware Sensor Node Architecture Problem: radio often simply relays packets in multihop network  NS-2 simulation: 1000x1000 terrain, 30 nodes, DSR, CBR traffic from random SRC and DEST Traditional approach: main CPU woken up, packets sent to it across serial bus  power hungry computing and communication operations Communication Subsystem Radio Modem GPS Micro Controller Rest of the Node CPU Sensor Multihop Packet Traditional Approach Action% of received packets ACCEPT34.300 FORWARD65.567 DROP0.133

26. …zZ Z Energy Impact of Our Packet Forwarding Architecture Simple packet processor in the radio Packets are redirected as low in the protocol stack as possible Measured + simulated results using Atmel AVR and Triscend E520 with Rockwell Nodes  Lower latency (44 ms) once Pr FW > 3% Pr AC  Lower energy (savings) Average of 17.5 mJ/packet with Atmel AVR Average of 7.5 mJ/packet with Triscend E520 Communication Subsystem Radio Modem GPS Micro Controller Rest of the Node CPU Sensor Multihop Packet Our Approach

27. Energy Savings Difference in Energy consumption is also dominated by the Serial port crossing penalty and the relation (  ) of the power consumption of the Microcontroller and the Sensor CPU Energy difference due to ACCEPT Energy difference due to FWD Serial Port crossover penalty CPUMCU  WINS (351mW)Atmel AVR (15mW)23.4 WINS (351mW)E520 (470mW)0.747 E diff 1167*P MCU 16*P MCU For Simulation Data

28. Near-term (Summer) Plans Power-management of CPUs  Power analysis of SA-2 with variable voltage Soon getting SA-2 board being donated by Intel  Finish power-aware API Power-management of radios  Further development of energy-aware packet scheduling  Better understanding its utility  So far power management under traffic variations only Next: combine traffic and channel variations  Some validation using prototype, perhaps using FPGA Coordinated CPU& radio power management Modeling  ARL sensor data and algorithms Incorporate into sensorsim  Combined modeling of CPU and radio power consumption (Joulestrack + Sensorsim?) Node architecture  SA-2 and TMS320C55

29. The End!