1. Controls renovation workshop Standardized Hardware Modules Javier Serrano, AB-CO-HT MJD 54803

2. Outline Motivations Work Packages  Scope  Objectives  Budget Estimation  Human Resources Conclusions Summary table 2

3. Outline Motivations Work Packages  Scope  Objectives  Budget Estimation  Human Resources Conclusions Summary table 3

4. Introduction: the Controls HW KitControls HW Kit Both VME and PCI. Includes analog and digital I/O, field busses (incl. timing), stepping motor control and misc (pulse repeaters, adapters…). For each component, we (will) support:  Hardware: user manual, help in debugging…  Device driver with I/O emulation for Linux, with documentation.  A test program on top of the driver, with documentation.  A library on top of the driver, with documentation and usage examples. We don’t support anyone bypassing this library.  A test program on top of the library, with documentation.  A test procedure.  An installation procedure.  A wiki with known issues and the level of support offered for a given module (if different from “complete support”).  Version management of all HW and SW above.  All of the above are based on templates and standard procedures. This is of course important for maintainability.

5. Motivations Standard hardware modules  Obsolescence problems Some solutions are more than 30 years old → poor reliability. Detailed knowledge has been lost: CAMAC, PSB matrix... → poor support.  Quality of support from some companies is poor. Drivers  Reduced maintenance team. Need to reduce maintenance costs by standardizing. A standard approach for drivers/libraries and test programs is being defined. Big upgrade operation needed after that, with help from industry and temporary labour.

6. Outline Motivations Work Packages  Scope  Objectives  Budget Estimation  Human Resources Conclusions Summary table 6

7. General strategy Use the new FPGA Mezzanine Card (FMC) Vita 57 standard. Design/buy FMCs which can be placed on VME, PCI, PCIe… carriers. In the following, we assign a work package per module category, which includes both SW and HW development.  WP1: Analog input.  WP2: Analog output.  WP3: Digital I/O with interrupts.  WP4: timing and field busses.  WP5: stepping motor control.  WP6: misc developments, including carriers. Special work package (WP7) for the migration of legacy device drivers to the new front end platforms. Assumptions for budgeting and manpower: a designer designs one module in 3 FTE months, a software developer takes roughly 2 FTE months to do his/her part, and the whole thing including prototypes costs 30k. Following slides show proposed state of HW kit in two years, with needs for work highlighted in orange.

8. WP1: Analog input Scope: cover low, medium and high speed sampling in both VME and PCI. Objectives HR and budget: 14 mm (only SW for VD80 and SIS3300) and 60 kCHF. 8 Module name FormatNumber of channels BitsSampling speed Unit price (CHF) When VMOD 12E16 Modulbus161210ks/s600 (+525 for VME carrier) Now VD80VME16 200 ks/s4.2k03/2009 SIS3300 family VME814-12100-250 Ms/s 5.5-6.8k03/2009 FMC1FMC8161Ms/s500 (+500 for carrier) 12/2009 FMC2FMC414100 Ms/s500 (+500 for carrier) 12/2009 Agilent (Acqiris) series PCI/CPCI1-2-48-12-14Up to 8 Gs/s ManyNow

9. WP2: Analog output Scope: cover low and high speed analog waveform generation in both VME and PCI. Objectives HR and budget: 9 mm and 30 kCHF (CVORB and CVORG already in the proto phase). 9 Module name FormatNumber of channels BitsSampling speed Unit price (CHF) When VMOD 12A2 Modulbus412100ks/s450 (+525 for VME carrier) Now CVORBVME16 200 ks/s1k03/2009 CVORGVME214100 Ms/s1k04/2009 FMC3FMC4161Ms/s500 (+500 for carrier) 06/2009

10. WP3: Digital I/O with interrupts Scope: give digital (parallel) I/O with interrupts to PCI and VME platforms. Objectives NB: the CVORA does much more than mere parallel I/O. This extra functionality can also be implemented in FMC4. FMC4 can also potentially support synthetic B Train generation and stepper motor control. HR and budget: 7 mm and 30 kCHF (only SW for CVORA). 10 Module name FormatNumber of bits InterruptsUnit price (CHF) When VMOD TTL Modulbus16No450 (+525 for VME carrier) Now CVORAVME32No1k03/2009 FMC4FMC16Yes1k12/2009

11. WP4: Timing and field busses Scope: support GMT, RS232, RS422, RS485, MIL1553, White Rabbit (WR) and WFIP in both VME and PCI. HR and budget: 21 mm (only SW for first three) and 90 kCHF. NB: CTRI/P/V will continue to be a fully supported standard solution for GMT. WR and GMT will be inter-operable. Module nameFormatField busUnit price (CHF) When CTRI/P/VPCI/PMC/VMEGMT1kNow Alstom CC14xPMCWFIP?Now IP-OCTAL232IP mezzanineRS232 (8 channels) 525 (+780 for VME carrier) Now for VME, 04/2009 for PCI IP- OCTAL422/485 IP mezzaninesRS422 /485 (8 channels) 600 (+780 for VME carrier) Now for VME, 04/2009 for PCI CBMIAPCIMIL15531k03/2009 WR1uTCAWR switch5k12/2009 WR2PCIWR master1k12/2009 FMC5FMCWR slave1k06/2010

12. WP5: Stepping motor control Scope: give stepping motor control to PCI and VME platforms. Objectives HR and budget: 2 mm and 0 CHF (if stepper motor control not done with FMC4). 12 Module nameFormatUnit price (CHF)When VMOD MTCModulbus480 (+525 for VME carrier) 06/2009

13. WP6: Misc developments Scope: “the rest”. Objectives HR and budget: 35 mm and 210 kCHF. Module nameFormatWhat it doesUnit price (CHF) When PCI1PCIPCI carrier for FMCs50006/2009 VME1VMEVME carrier for FMCs50006/2009 FMC6FMCFine delay card50012/2009 OASIS13U?OASIS impedance adapter 20006/2010 PULSE13U?New blocking pulse repeaters, with time stamps 10006/2010 PCIe1PCIePCIe carrier for FMCs50012/2010 FMC7FMCDDS50012/2010

14. WP7: migration of drivers to new platforms Some 30 drivers concerned. Not all of them will need rewriting depending on upgrade strategies. Assume half of them need rework → 30 mm of work. 14

15. Outline Motivations Work Packages  Scope  Objectives  Budget Estimation  Human Resources Conclusions Summary table 15

16. Conclusions We need to revise quickly our standard kit of HW modules to deal with lack of support due to obsolescence and also to support the new PCI platforms. A global schedule is proposed over two years:  Immediate deliverables: MIL1553 master in PCI. VD80 (100 ks/s 16 channel sampler in VME). CVORB (GFAS replacement) in VME.  Need in-depth discussion with clients to fine-tune further milestones. Global estimated cost: 72 mm and 834 kCHF.

17. Summary table 17 20092010Totals SW HR17 mm13 mm30 mm HW HR27 mm15 mm42 mm SW budget342k (30 mm)(*)72k (12 mm)414k HW budget270k150k420k Grand total: 72 mm and 834 kCHF over 2 years (*) 12 mm @ 6k/mm (UPAS) + 18 mm @ 15k/mm (industry).