2. Integrated Circuit Technology
EE40
6 August 2008

3. Integrated Circuit Fabrication
Goal:
Mass fabrication (i.e. simultaneous fabrication) of many “chips”, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors
Methods for Top Down processing:
Addition of material
Subtraction of unwanted material
Thermal/Doping modification of material
Analogous to making Gingerbread men… yeah.

4. Still in Infancy: Bottom-up Processing
Cheap electronics
Organic Printed Electronics – Process is serial (slow) and resolution is poor
High-performance transistors
Catalyzed Growth – Nanotubes/Nanowires hard to place and grow in the desired direction.

5. Standard Materials Set
Si substrate – selectively doped in various regions
SiO2 insulator – MOST IMPORTANT component
Polycrystalline silicon – used for the gate electrodes
Metal contacts and wiring

6. Si Substrates (Wafers)
Why are wafers round?
We pull crystalline-Si out of hot ingots, starting with a seed crystal.
Crystalline-Si exhibits the best electronic properties for transistors.
300 mm
Typical wafer cost: $50 (!!!)
Sizes: 150 mm, 200 mm, 300 mm diameter
“notch” indicates
crystal orientation

7. Makes the Silicon N-type or P-type
Doping
Makes the Silicon N-type or P-type

8. Adding Dopants into Si
Suppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an “ion gun” called an ion implanter, into the surface of the wafer.
Eaton HE3
High-Energy
Implanter,
showing the
ion beam
hitting the
end-station
Typical implant energies are in the range keV. After the ion implantation, the wafers are heated to a high temperature (~1000oC). This “annealing” step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites.

9. Ion Implanter  F = q( v B ) wafer spinning wafer holder
e.g. AsH3 gaseous source
As+, AsH+, H+, AsH2+
analyzer magnet
F = q( v B )
Ion
source
Energy: 1 to 200 keV
Dose: 1011 to1016/cm2
Inaccuracy of dose: <0.5%
Nonuniformity: <1%
Throughput: ~60 wafers/hr 
ion beam
resolving aperture
accelerator
As+
wafer
translational
motion
spinning wafer
holder

10. Dopant Diffusion
The implanted depth-profile of dopant atoms is peaked.
In order to achieve a more uniform dopant profile, high- temperature annealing is used to diffuse the dopants
Dopants can also be directly introduced into the surface of a wafer by diffusion (rather than by ion implantation) from a dopant-containing ambient or doped solid source
dopant atom
concentration
(logarithmic
scale)
as-implanted profile
depth, x

11. Fixes the damage caused by ion implantation.
Annealing
Fixes the damage caused by ion implantation.

12. Rapid Thermal Annealing (RTA)
Sub-micron MOSFETs need ultra-shallow junctions (xj<50 nm)
 Dopant diffusion during “activation” anneal must be minimized
Short annealing time (<1 min.) at high temperature is required
Ordinary furnaces (e.g. used for thermal oxidation and CVD) heat and cool wafers at a slow rate (<50oC per minute)
Special annealing tools have been developed to enable much faster temperature ramping, and precise control of annealing time
ramp rates as fast as 200oC/second
anneal times as short as 0.5 second
typically single-wafer process chamber:

13. Rapid Thermal Annealing Tools
There are 2 types of RTA systems:
Furnace-based
steady heat source + fast mechanical wafer transport
Lamp-based
stationary wafer + time-varying optical output from lamp(s)
Furnace RTA
A.T. Fiory, Proc. RTP2000
Lamp RTA

14. Film Growth
Allows formation of high-quality films (usually SiO2) necessary for low leakage.

15. Formation of Insulating Films
The favored insulator is pure silicon dioxide (SiO2).
A SiO2 film can be formed by one of two methods:
Oxidation of Si at high temperature in O2 or steam ambient
Deposition of a silicon dioxide film
Applied Materials low-pressure chemical-vapor deposition (CVD) chamber
ASM A412
batch
oxidation
furnace

16. Thermal Oxidation or “dry” oxidation “wet” oxidation
Temperature range:
700oC to 1100oC
Process:
O2 or H2O diffuses through SiO2 and reacts with Si at the interface to form more SiO2
1 mm of SiO2 formed consumes ~0.5 mm of Si
oxide
thickness
time, t

17. Example: Thermal Oxidation of Silicon
Silicon wafer, 100 mm thick
Thermal oxidation grows SiO2 on Si, but it consumes Si, so the wafer gets thinner. Suppose we grow 1 mm of oxide:
99 mm thick Si, with 1 mm SiO2 all around  total thickness = 101 mm
99mm
101mm

18. Oxidation Rate Dependence on Thickness
The thermal oxidation rate slows with oxide thickness.
Consider a Si wafer with a patterned oxide layer:
Now suppose we grow 0.1 mm of SiO2:
SiO2 thickness = 1 mm Si
SiO2 thickness = 1.02 mm
SiO2 thickness = 0.1 mm
Note the 0.04mm step in the Si surface!

19. Selective Oxidation Techniques
Window Oxidation
Local Oxidation (LOCOS)

20. Deposition
Allows you to put down conformal films that cannot be grown from the substrate.

21. Chemical Vapor Deposition (CVD) of SiO2
“LTO”
“TEOS”
Temperature range:
350oC to 450oC for silane
~700oC for TEOS
Process:
Precursor gases dissociate at the wafer surface to form SiO2
No Si on the wafer surface is consumed
Film thickness is controlled by the deposition time
oxide
thickness
time, t

22. Conformality CVD Properties: Can be deposited on top of anything.
Can follow ups & downs (topography) of pre-existing layers

23. Lithographic Patterning
Film-camera-like process that lets you define shapes in your thin films.

24. Patterning the Layers Planar processing consists of a sequence of
additive and subtractive steps with lateral patterning
oxidation
deposition
ion implantation
etching
lithography
Lithography refers to the process of transferring a pattern
to the surface of the wafer
Equipment, materials, and processes needed:
A mask (for each layer to be patterned) with the desired pattern
A light-sensitive material (called photoresist) covering the wafer so as to receive the pattern
A light source and method of projecting the image of the mask onto the photoresist (“printer” or “projection stepper” or “projection scanner”)
A method of “developing” the photoresist, that is selectively removing it from the regions where it was exposed

25. Areas exposed to UV light are susceptible to chemical removal
Photoresist Exposure
A glass mask with a black/clear pattern is used to expose a wafer coated with ~1 m thick photoresist
UV light
Mask
Lens
Image of mask appears here
(3 dark areas,
4 light areas)
Mask image is demagnified by nX
photoresist
Si wafer
“10X stepper”
“4X stepper”
“1X stepper”
Areas exposed to UV light are susceptible to chemical removal

26. Exposure using “Stepper” Tool
field size increases
with technology
generation
scribe line 1 2
wafer
images
Translational
motion

27. Commercial Stepper Tool (ASM Lithography)

28. Photoresist Development
Solutions with high pH dissolve the areas which were exposed to UV light; unexposed areas are not dissolved
Exposed areas of
photoresist
Developed
photoresist

29. Lithography Example Mask pattern (on glass plate)B A
(A-A and B-B)
Look at cuts (cross sections) at various planes

30. “A-A” Cross-Section
The resist is exposed in the ranges 0 < x < 2 m & 3 < x < 5 m:
mask
pattern x [ m m] 1 2 3 4 5 x [ m m] 1 2 3 4 5
resist
The resist will dissolve in high pH solutions wherever it was exposed:
resist after development x [ m m] 1 2 3 4 5

31. Pattern Transfer by Etching
In order to transfer the photoresist pattern to an underlying film, we need a “subtractive” process that removes the film, ideally with minimal change in the pattern and with minimal removal of the underlying material(s)
Selective etch processes (using plasma or aqueous chemistry)
have been developed for most IC materials
photoresist
SiO 2
First: pattern photoresist Si
We have exposed mask pattern, and developed the resist
etch stops on silicon (“selective etchant”)
oxide etchant … photoresist is resistant.
Next: Etch oxide
only resist is attacked
Last: strip resist
Jargon for this entire sequence of process steps: “pattern using XX mask”

32. Photolithography quartz plate chromium 2 types of photoresist:
positive tone:
portion exposed to light will be dissolved in developer solution
negative tone:
portion exposed to light will NOT be dissolved in developer solution
from Atlas of IC Technologies by W. Maly

33. Projection Printing Considerations
minimum feature size  lm :
Intel’s Lithography Roadmap
Small lm is desired!

34. Depth of Focus
depth of focus  Dz :
Large Dz is desirable.

35. Remove material that you don’t want
Etching
Remove material that you don’t want

36. Etching: Ion vs. Wet better control of etched feature sizes
from Atlas of IC Technologies by W. Maly
better control of etched feature sizes
better etch selectivity

37. RIE-based Stringers / Spacers
Leftover material must be removed by overetching

38. D’oh! Stringers

39. Example Process Flow
CMOS Technology

40. CMOS Technology Challenge: Build both NMOS & PMOS transistors
on a single silicon chip
NMOSFETs need a p-type substrate
PMOSFETs need an n-type substrate
 Requires extra process steps!
oxide
p-well
n-type Si n+ p+

41. Conceptual CMOS Process Flow
n-type wafer
*Create “p-well”
oxide p+
p-well n+
n-type Si
Grow thick oxide
*Remove thick oxide in transistor areas (“active region”)
Grow thick oxide
*Remove thick oxide in transistor areas (“active region”)
Grow gate oxide
Deposit & *pattern poly-Si gate electrodes
*Dope n channel source and drains (need to protect PMOS areas)
*Dope p-channel source and drains (need to protect NMOS areas)
Deposit insulating layer (oxide)
*Open contact holes
Deposit and *pattern metal interconnects
At least 3 more masks, as
compared to NMOS process

42. Additional Process Steps Required for CMOS
1. Well Formation
Top view of p-well mask
(dark field)
Cross-sectional view of wafer
SiO2
n-type Si
boron
p-well
Before transistor fabrication, we must perform the following process steps:
grow oxide layer; pattern oxide using p-well mask
implant phosphorus; anneal to form deep p-type regions

43. 2. Masking the Source/Drain Implants
“Select p-channel”
We must protect the n-channel devices during the boron implantation step, and
We must protect the p-channel devices during the arsenic implantation step
“Select n-channel”
Example: Select p-channel
boron
photoresist
oxide
p-well
n-type Si n+ p+

44. Forming Body Contacts Modify oxide mask and “select” masks:
Open holes in original oxide layer, for body contacts
Include openings in select masks, to dope these regions
oxide
p-well
n-type Si n+ p+

45. Select Masks N-select: P-select: oxide p-well n-type Si n+ oxide

46. Micro Electro Mechanical Systems
Example MEMS Flow
Micro Electro Mechanical Systems

47. MEMS Switch Contact Areas: 0.4x0.4 um2 to 8x8 um2
Source
Drain
Gate(s)
Drain
Contact Areas: 0.4x0.4 um2 to 8x8 um2
Devices from 50 um to 250 um long

48. Process Flow Elec0 Layer Pre-alignment Isolation Si Substrate
Dimple hole
Main Sacrificial (LTO)
Pattern Elec0
Pre-alignment
Isolation Growth
6000A Low Temp Oxide
1000A Stoichiometric Silicon Nitride
Poly 0 Deposition
Poly 0 Formation
RIE to isolation w/ overetch
Main Sacrificial Deposition
5500A Low Temp Oxide
Dimple Formation
DRIE to Isolation or timed DRIE

49. Process Flow Fine refill sacrificial (HTO) Fine Sacrificial Deposition
Anchor holes
Elec1 Layer
Sacrificial Release
Fine Sacrificial Deposition
650A High Temp Oxide
Anchor Formation
DRIE to isolation layer
Poly 1 Deposition
615C n-doped
Poly 1 Formation
RIE etch to Main Sac
Sacrificial Release
HF:HCl 20’ then critical pt. dry
Process Finished