1. Optimality, Scalability and Stability study of Partitioning and Placement Algorithms Jason Cong, Michail Romesis, Min Xie UCLA Computer Science Department This work is partially supported by Semiconductor Research Corporation and National Science Foundation

2. 2 Overview n Motivation and related work n Our contribution u Construction of Partitioning Examples with Known Upper bound u Construction of Placement Examples with Known Upper bound u Optimality, Scalability and Stability study n Conclusions and future work

3. 3 Overview n Motivation and related work n Our contribution u Construction of Partitioning Examples with Known Upper bound u Construction of Placement Examples with Known Upper bound u Optimality, Scalability and Stability study n Conclusions and future work

4. 4 Motivation Partitioning u Significant progress in partitioning during the mid-to- late 90’s u No significant improvement in the last 5 years u Have we reached a plateau?

5. 5 Motivation Placement n Lack of significant progress in wirelength reduction u Rate of reduction is about 5-10% every 2-3 years u Latest developments in placement differ mainly in runtime F Capo [A. Caldwell et al, 2000] F Dragon [M. Wang et al, 2000] F Mongrel [S. Hur et al, 2000] F mPL [T. Chan et al, 2000] F mPG [C. Chang et al, 2002] n How much is the room for further improvement?

6. 6 Motivation n Most work compare only with known heuristics u Use real design based benchmarks F ISPD98 [C. Alpert 1998] F WSI [D. Ghosh et al, 1997] u Use synthetic benchmarks F circ and gen [M. D. Hutton et al, 1998] F gnl [D. Stroobandt et al, 2000] n Little understanding about the divergence from the optimal

7. 7 Related Work n Quantified Suboptimality of VLSI Layout Heuristics [L. Hagen et al, 1995] u Construct scaled instance with known upperbound from an initial problem x xxx xxx xxx ? u Over 10% area suboptimality in TimberWolf u Notable wirelength suboptimality in GORDIAN-L u Significant improvement was possible for placement and partitioning u But test cases are small, the largest netlist is less than 40K

8. 8 Related Work n Optimality and Scalability of Existing Placement Algorithms [C. Chang et al, 2003] u Construct instances with known optimal using the characteristic of the original problem ? u Existing placement algorithms can be 70% to 150% away from the optimal  Average solution quality deteriorates by an additional 4% to 25% when the problem size increases by a factor of 10  All the connections are local, no global connections

9. 9 Overview n Motivation and related work n Our contribution u Construction of Partitioning Examples with Known Upper bound u Construction of Placement Examples with Known Upper bound u Optimality, Scalability and Stability study n Conclusions and future work

10. 10 BEKU Construction Example n Cutsize improved to 4 after FM Input: t = 16, D={12,8} B = 5 n Generate 9 2-pin nets that do not cross the partition line C D B A P1P1 P2P2 n Create two partitions of size 8 n Generate 3 2-pin nets that cross the partition line n Generate 6 3-pin nets that do not cross the partition line n Generate 2 3-pin nets that cross the partition line n Cutsize = 5

11. 11 Construction of Multiway Partitioning Examples with Known Upper Bounds (MEKU) m n Divide the nodes into m partitions of equal size B n Create B nets that cross at least two partitions. The remaining nets stay in one partition n Improve by multiway FM

12. 12 BEKU and MEKU Suite n 2-way partitions occupy 45-55% of the total area n 8-way partitions occupy 11.8-13.3% of the total area URL : http://cadlab.cs.ucla.edu/~pubbench/partitioning//

13. 13 Tested three State-of-the-Art Partitioning Tools n hMetis [G. Karypis et al, 1997] u Based on multilevel framework u MHEC and FC clustering algorithms u Variations of FM for refinement at each level n MLPart [A. Caldwell et al, 2000] u Based on multilevel framework u Different algorithms for coarsening (PinEC) and refinement (VRW) n Flare [J. Cong et al, 2000] u Two-level hierarchy created by the ESC clustering algorithm u Based on the LR bipartitioning engine and the PM multiway partitioning framework

14. 14 Experimental Results on BEKU n MLPart produces the best results (very close to our estimated upper bound), and Flare the worst n The value of the bound (as a percentage of nets) influences the quality of hMetis and Flare

15. 15 Experimental Results on BEKU n The runtime scale well (almost linearly) n Flare runs out of memory when problem size exceeds 1M nodes

16. 16 Experimental Results on MEKU n hMetis is worse by only 2% when the initial bound is 30%, but the gap increases to 18% for a bound of 35% n MLPart does not support multiway partitioning

17. 17 Placement Examples with Global Connections n Produced by Dragon on ISPD98 n The wirelength contribution from global connections can be significant! n Need to consider the impact of global connections

18. 18 Placement Examples with Global Connections only n Each net connects either a row or column n Obvious upper bound u Sum the length of each row and column n Similar to datapath examples

19. 19 Placement Examples with Non-local Connections n Extend PEKO [ C.Chang 2003] by introducing non-local nets to mimic global connections u All the modules are of equal size, and there is no space between rows and adjacent modules i  *d i  i u For nets of degree i,  *d i  of them are generated by randomly conneting i modules, the rest are generated optimally as in PEKO

20. 20 Placement Examples with Non-local Connections Input : t = 64, D = {d 2 =34,d 3 =20,d 4 =7,d 5 =4,d 6 =2, d 7 =1}  =0.2 Total WL = 160 Generate 28 2-pin optimally Generate 6 2-pin randomly Generate 16 3-pin optimally Generate 4 3-pin randomly Generate 6 4-pin randomly Generate 1 4-pin randomly Generate 4 5-pin optimally Generate 2 6-pin optimally Generate 1 7-pin optimally

21. 21 G-PEKU Suite n Module number extracted from ISPD98 URL: http://cadlab.cs.ucla.edu/~pubbench/peku.htm

22. 22 PEKU Suite n Module number t and NDVs extracted from ISPD98 n Remove connections with pads n Vary  from 0 to 10% n 15% white space by expanding one dimension of the chip

23. 23 PEKU Suite URL: http://cadlab.cs.ucla.edu/~pubbench/peku.htm

24. 24 Tested four State-of-the-Art Placers n Capo [A. Caldwell et al, 2000] u Based on multilevel partitioner u Aims to enhance the routability n Dragon [M. Wang et al, 2000] u Uses hMetis for initial partition u SA with bin-based swapping n mPL [T. Chan et al, 2000] u Nonlinear programming on the coarsest level u Goto based relaxation n mPG [C. Chang et al, 2002] u Uses FC clustering and hierarchical density control u Incremental A-tree for routability

25. 25 Experimental Results on G-PEKU n The gap between their solutions and the upper bound varies between 79% and 102% in the worst case n Another validation that there is significant room for improvement for the placement problem

26. 26 Experimental Results on PEKU n mPL’s QR increases when  is increased from 0 to 0.75%, while for the other three placers, QRs are steadily decreasing n Absolute value of the QRs may not be meaningful, but it helps to identify the technique that works best under each scenario

27. 27 Overview n Motivation and related work n Our contribution u Partitioning Examples with Known Upper bound u Placement Examples with Known Upper bound u Optimality, Scalability and Stability study n Conclusions and future work

28. 28 Conclusions Bipartitioning techniques seem fairly mature  The best available algorithms perform and scale very well on examples by our construction The best available multiway partitioning algorithms do not perform equally well  The worst divergence from upperbound is 18% by hMetis There is still significant room for improvement in circuit placement u Existing placement algorithms may produce solutions far away from the optimal (or upper bound) u Their effectiveness depends much on the characteristic of circuits

29. 29 Future Work n Construction of more synthetic examples u Measure routability optimality u Measure timing optimality n Understand the deficiencies of existing algorithms using these examples n Guide the development of new VLSI CAD algorithms

30. 30 Acknowledgement n Prof. I. Markov for providing Capo’s latest version n Prof. S. Lim for providing Flare’s latest version n X. Yuan for providing the data of mPG n J. Shinnerl and K. Sze for providing the experimental data of mPL

31. 31 THE END THANK YOU