1. Some Irradiation Results from a Chip in UMC018 Technology Peter Fischer for Christian Kreidl Heidelberg University P. Fischer, ziti, Heidelberg

2. Summary  UMC018 Chip was irradiated with X-rays to 7.5Mrad  No degradation after annealing  Strange effects around 1.2Mrad  Work done in the frame of the DEPFET project  Measurements by Christian Kreidl  Chip by Ivan Peric P. Fischer, ziti, Heidelberg

3. DCD1 Chip The Chip  DCD1 = DEPFET Current Digitizer  Readout Chip for DEPFET Sensor columns current memory cells to subtract pedestal DEPFET Sensor goes here… 8 bit ADCs using current memory cells P. Fischer, ziti, Heidelberg

4. More Details... Generate ADC + memory cell control signals Clock Divider 600MHz ADC Steering Signals 2 ADCs Sample ADC Output Logic ADC result calculation, MUX sync for FPGA, Switcher Serializer 3 x 6 lines per pixel Current Subtract Regulated Cascode Sampling Test Injection current Monitoring Pad P. Fischer, ziti, Heidelberg

5. Chip Layout & Design  UMC 0.18µm technology, 2 x MiniASIC size  ADC in radhard layout (enclosed NMOS, guard rings)  Digital part without any precautions  72 inputs P. Fischer, ziti, Heidelberg

6. Pixel Layout bump pad with 60µm opening two 8 bit algorithmic current mode ADCs working interleaved regulated cascode test injection digital stuff (conservative layout) Size x: 180µm Size y: 110µm P. Fischer, ziti, Heidelberg

7. Chip Test Setup  Chip glued & bonded to PCB – no cover  Readout via USB P. Fischer, ziti, Heidelberg

8. Irradiation Facility in Karlsruhe  60 keV X-Ray tube at Institut für Nuclear Physics, Karlsruhe  100-250 krad/h (depending on distance), calibrated setup  Thanks to Dr. Simonis, Mr. Dierlamm and Mr. Ritter for help! P. Fischer, ziti, Heidelberg

9. Irradiation  Dose: 31h @99.5 krad/h (d=180mm)= 3.1 Mrad 18h @241 krad/h (d=100mm)= 4.4 Mrad Total= 7.5 Mrad  DCD Operation Mode clock running permanently control registers loaded every 30s with default values (precaution against SEU)  Measurements (while tube is on!): current consumption on VDD (= analog + digital) on selected pixels: - Current memory cell operating range - ADC characteristics - Test injection current value P. Fischer, ziti, Heidelberg

10. Current consumption  Total supply current (analog + digital)  Current rises until 1.2Mrad, then settles to pre-rad value Probably bit flip In Bias DACs 1.2Mrad = pre-rad P. Fischer, ziti, Heidelberg

11. Current Memory Cells  Cell keeps input voltage constant within ± 10µA P. Fischer, ziti, Heidelberg

12. ADC Characteristic (ADC value vs. Injection DAC)  Test current injected via ON-CHIP injection DAC  SEUs during measurement (more at 1.2Mrad !)  most effects @<1.2Mrad, some ADCs BROKEN  after 7Mrad and 6 days annealing: back to pre-rad behavior Many SEUs Pixel 59Pixel 71 BROKEN @ 1.2Mrad 0 Mrad = after anneal. 7 Mrad P. Fischer, ziti, Heidelberg

13. Test Injection Current vs. DAC value  Test injection current is ok (not dead). Some variation. P. Fischer, ziti, Heidelberg

14. ADC Histograms  Plot deviation from straight line  45nA (@0)  70nA (@1.2-7 Mrad)  44nA (7 day anneal) P. Fischer, ziti, Heidelberg

15. ADC noise map  All ADCs back to initial values after anneal Readout problems due to setup P. Fischer, ziti, Heidelberg

16. Summary  No degradation after 7Mrad of 60keV X-rays  Strange effects at 1.2 Mrad (power higher, ADC dead) P. Fischer, ziti, Heidelberg

17. Thank you! P. Fischer, ziti, Heidelberg

18. Bump Bonding Status in HD Peter Fischer, ziti, Uni Heidelberg for Christian Kreidl P. Fischer, ziti, Heidelberg

19. Reminder  We do gold stud bumping: Create a gold sphere on bonder Place ball on chip, Thermocompress, rip off wire Place all bumps Flip & press & heat (~50g / bump) Can put bumps on both sides to reduce forces Can put isotropic glue with conducting particles  Key parameters: Diameter of balls~ 45µm Min. bond pad size~ 60µm Min pitch~ 100µm  Advantages: single chip (prototype) process, in house, cheap  Drawbacks: sequential, limited # of pads, large force, possible destruction of electronics under pad, need hard substrate, no rework P. Fischer, ziti, Heidelberg

20. Tests with Dummy Chips  Aluminum on Silicon structures  Substrate and ‘chip’  Trace pattern to check contact & shorts SuS@Uni-Heidelberg P. Fischer, ziti, Heidelberg

21. Chip with Bumps P. Fischer, ziti, Heidelberg

22. Flipped Assemblies  80g/bump: all bumps connected, no shorts  20g/bump: 4 of 6 snakes connected, chip fell off P. Fischer, ziti, Heidelberg SuS@Uni-Heidelberg

23. Large Size Module  Mechanical demonstrator of ILC vertex detector module no electrical tests check how to handle a large silicon device check how low pitch flipping works  16 DCD (dummy) chips  36 Switcher (dummy) chips  11,9 cm x 1,6 cm  No electrical test possibilities 2 x 18 ‘Switcher’ chips 8 ‘DCD’ chips P. Fischer, ziti, Heidelberg

24. Placing Chips Close to Each Other (side view)  Switcher (dummy) chips 164 bumps each1,4mm x 5,8mm  60g/bump = 9,8kg/chip SuS@Uni-Heidelberg Edge of flip tool SuS@Uni-Heidelberg P. Fischer, ziti, Heidelberg

25. ILC Mechanical Sample SuS@Uni-Heidelberg P. Fischer, ziti, Heidelberg

26. Minimum gap SuS@Uni-Heidelberg 50µm gap P. Fischer, ziti, Heidelberg

27. Module End  224 bumps/chip, 1.35mm x 4.95mm, 13.4kg/chip SuS@Uni-Heidelberg 200µm gap P. Fischer, ziti, Heidelberg

28. Full sample  One module populated with 52 chips  No failures ! SuS@Uni-Heidelberg P. Fischer, ziti, Heidelberg

29. Effort  Bonding process: cleaning, mounting, aligning, bumping Switcher:11min DCD:13min  Flipping process: pickup, aligning, thermocompression 9 min  2 days of work including learning  Improvements: build better mounting device for single chip bumping (mechanical clamp) P. Fischer, ziti, Heidelberg

30. Thank you! P. Fischer, ziti, Heidelberg

31. ADC Design in Heidelberg Peter Fischer, ziti, Uni Heidelberg ADC Design: Ivan Peric P. Fischer, ziti, Heidelberg

32. Content  Algorithmic / Pipeline ADC principles  Voltage vs. Current Mode  ADC in DEPFET readout chip  Reminder: ADC of David Muthers (Kaiserslautern)  Comparison of figures of Merit P. Fischer, ziti, Heidelberg

33. Algorithmic (Cyclic) ADC  Idea: Compare signal to half scale  generate BIT If BIT = 1: subtract half scale Multiply result by two Restart over again  Every cycle produces a new bit  Very popular architecture  Resolution limited by precision of Compare / Subtract / Multiply  Comparator requirements are relaxed by two threshold per stage (and some error correction) P. Fischer, ziti, Heidelberg

34. ADC Stage P. Fischer, ziti, Heidelberg 34 ADCDAC + + - k Bit

35. Pipeline ADC  Shift value through many stages  Can process one new value per cycle  More hardware  Faster  Can scale cells for lower precision in later cells P. Fischer, ziti, Heidelberg Stage 1Stage 2 Stage m-1 Bit Alignment + RSD Correction 2222 V in Stage m

36. Voltage vs. Current  Signal can be voltage or current  Voltage: Often natural quantity delivered by circuit Comparison simple Add / Subtract & duplication with switched capacitor circuits Large swings Needs linear capacitors  Current May require U->I conversion Low swing operation Add / Subtract very simple Duplication with multiple current copy & add Can do with simple, small capacitors  No obvious winner P. Fischer, ziti, Heidelberg

37. Standard Current Memory Cell  Tracking phase: Diode connected transistor  Sample on gate capacitance  Drawbacks: Charge injection is signal dependent Low output resistance & current dependent Input potential current dependent Large storage cap (low leak) decreases speed P. Fischer, ziti, Heidelberg I in / I out

38. Pixel Layout P. Fischer, ziti, Heidelberg Two 8 Bit ADCs: Current memory cells, Comparators, Reference sources. Optimized, rad hard layout ADC timing signals (can be shared) 2 x Output Logic (shift registers…) Very conservative layout Using standard cells 110µm

39. ADC Characteristic P. Fischer, ziti, Heidelberg  8 Bit ADC output vs. injection DAC value

40. ADC Noise / INL  Plot deviation from ideal value for various inputs  Width mostly from noise in input stage P. Fischer, ziti, Heidelberg

41. Pipeline ADC (Design Study) P. Fischer, ziti, Heidelberg 41

42. Comparison: ADC from D. Muthers, Kaiserslautern  Voltage mode  Cyclic & Pipeline version  Early version used in TRAP chip P. Fischer, ziti, Heidelberg

43. Comparison P. Fischer, ziti, Heidelberg 43  FoM = P / 2 ENoB / f * 10 12 (small is good)  ADC from HD are VERY small HD, I mode Cyclic HD, I mode Pipeline KL, V mode Cyclic KL, V mode Pipeline Commercial IQ-Analog ENOBs~ 8 (9)~ 9 (design)~ 9.2 @ f in =5MHz ~ 9.79 speed6 MS/s25 MS/s10 MS/s75 MS/s80 MS/s Power1 mW4.5 mW9.5 mW30 mW8 mW Layout area ~3.000 µm 2 (rad hard) ~10.000 µm 2 (rad hard) 110.000 µm 2 (non rad hard) > 200.000 µm 2 (non rad hard) 210.000 µm 2 (0.13µm) AdditionallyShift register Delay registers ??? - FoM [pJ/conv] 0.650.351.60.480.2

44. Thank you! P. Fischer, ziti, Heidelberg

45. Simple Serial Data Driver Peter Fischer, ziti, Uni Heidelberg P. Fischer, ziti, Heidelberg

46. Goal  Study a serial driver suited to directly drive an FPGA  Find out how Complex Large Power hungry it is.  Later: study copper transmission: how long can we go ? How fast can we go ? For which type of cable ? for which power requirement ? P. Fischer, ziti, Heidelberg

47. Design choices  Use (free) Aurora protocol from Xilinx  No back channel  No channel bonding  Minimize protocol engine  Use radiation hard library for a test P. Fischer, ziti, Heidelberg

48. Aurora – Protocol  Physical layer interface – electrical levels, clock encoding, symbol coding  Channel initialization and error handling  Link layer: Beginning / End of data IDLE Clock compensation 8B/10B encoding  Arbitrary data format, Data packets with arbitrary length  4 Phases: Initialization Synchronization of receiver clock (send some syncs) Data transmission Idle  Must inject clock compensation characters from time to time P. Fischer, ziti, Heidelberg

49. Components  FIFO: (data buffer)  Control FSM  8b/10b Encoder  Serializer  LVDS-Driver P. Fischer, ziti, Heidelberg

50. Initialisation P. Fischer, ziti, Heidelberg RESETTXRES_0 TXRES_1 zur Validierung ln_cnt < N+2 res_cnt < 3

51. Validation P. Fischer, ziti, Heidelberg VAL/A/VAL/R/ VAL/K/ CV_1CV_0 idle_cnt = 32 idle_cnt < 32 IDLE / Daten idle_cnt = 32 val_cnt = 60 von Initialisierung

52. Idle P. Fischer, ziti, Heidelberg IDLE/A/ IDLE/K/ CC_1 IDLE/R/ valid_data & even von Daten / Valid. Daten ccc_cnt = 10000 idle_cnt = 32 idle_cnt < 32 ccc_cnt = 10000 ev_cnt < 12

53. Data Transfer P. Fischer, ziti, Heidelberg SCP_0 CC_5_0 CC_5_1 PADDING CC_4 SCP_1 CC_2_0CC_2_1 CC_3 DATA ECP_0ECP_1 !valid_data !valid_data & even valid_data !valid_data & !even von IDLE / Val. Daten !valid_data IDLE

54. 8B/10B Kodierung  Bei der 8B/10B Kodierung können Sequenzen von maximal 5 aufeinander folgenden Nullen oder Einsen im seriellen Datenfluss entstehen.  Die Anzahl der Einsen pro Symbol unterscheidet sich maximal um zwei von der Anzahl der Nullen.  Zwischen zwei beliebigen Punkten im seriellen Datenfluss können maximal 6 Einsen mehr als Nullen (oder umgekehrt) vorkommen  Drei der Kontroll-Symbole, noch Kommas genannt, besitzen Bitmuster, die sonst bei keiner Kombination von 2 gültigen 10-Bit Symbolen vorkommen können. P. Fischer, ziti, Heidelberg

55. Serializer P. Fischer, ziti, Heidelberg  For simplicity: Realize in CMOS  Use shift register with load  Load generation most time critical  Several circuits have been compared  Minimal speed: 600 MHz  Reached 1.9GHz with standard cells

56. Test circuit on Xilinx Evaluation board  Generate Aurora compatible parallel data stream  Send to MGT serializer  Loopback via SATA cable  Receiver uses Aurora protocol P. Fischer, ziti, Heidelberg FSM, 8b/10b

57. Sample result: data transfer and Idle P. Fischer, ziti, Heidelberg

58. Synthesis with VST library P. Fischer, ziti, Heidelberg  First Using VST library

59. Simplification P. Fischer, ziti, Heidelberg 59  Try designs with NO clock compensation characters

60. Synthesis with Rad hard library P. Fischer, ziti, Heidelberg 60

61. Power estimation  No LVDS driver (which will dominate!)  Using VST Library  Rad hard ~ x4 P. Fischer, ziti, Heidelberg 61

62. Place & Route P. Fischer, ziti, Heidelberg  ~200 x 200mm 2 for rad had design

63. Next steps  Study realistic, fast LVDS driver  Study cable properties & modelling  First step: Simulated eye-diagram with Kaiserslautern driver + 10 cable, 24AWG (no pre-emphasis) P. Fischer, ziti, Heidelberg

64. Thank you! P. Fischer, ziti, Heidelberg