Presentation is loading. Please wait.

Presentation is loading. Please wait.

CSCI 3130: Automata theory and formal languages Andrej Bogdanov The Chinese University of Hong Kong Variants.

Similar presentations


Presentation on theme: "CSCI 3130: Automata theory and formal languages Andrej Bogdanov The Chinese University of Hong Kong Variants."— Presentation transcript:

1 CSCI 3130: Automata theory and formal languages Andrej Bogdanov http://www.cse.cuhk.edu.hk/~andrejb/csc3130 The Chinese University of Hong Kong Variants of Turing Machines Fall 2010

2 The Church-Turing Thesis “On Computable Numbers, with an Application to the Entscheidungsproblem” 1936: Section 9. The extent of the computable numbers All arguments [for the CT Thesis] which can be given are bound to be, fundamentally, appeals to intuition, and for this reason rather unsatisfactory mathematically. The arguments which I shall use are of three kinds: 1. A direct appeal to intuition 2. A proof of the equivalence of two definitions (In case the new definition has greater intuitive appeal) 3. Giving examples of large classes of numbers [languages] which are computable.

3 The multitape Turing Machine The transition may depend on the contents of all the cells Different tape heads can be moved independently control tape 1 … 010 tape 2 … 01 tape 3 … 100

4 The multitape Turing Machine Multiple tapes are convenient, e.g. one can serve as temporary storage … 010 … 01 … 100 … 110 … 100 q3q3 q7q7 0/1R☐/1R0/0L0/1R☐/1R0/0L … 011

5 The multitape Turing Machine Multitape Turing Machines are equivalent to single-tape Turing Machines M … 010 … 01 … 100  = {0, 1, ☐ } S … 01010##0#10   ’ = {0, 1, ☐, 0, 1, ☐, #}   #

6 Simulating a multitape TM We show how to simulate a multitape TM on an ordinary (single tape TM) To be specific, let’s do a 3-tape TM … x1x1 x2x2 xaxa xixi …… … y1y1 y2y2 ybyb yjyj …… z1z1 zczc zkzk … … Multitape TM Single-tape TM #x 1 x 2...x a...x i #y 1 y 2...y b...y j #z 1 z 2...z c...z k #  

7 Simulating a multitape TM Single-tape TM: Initialization … 010###  #  … 010 #w 1 w 2...w n # ☐ # ☐ #    w 1 w 2...w n S:S: On input w 1...w n : Replace tape contents by #w 1 w 2...w n # ☐ # ☐ #    1. Remember that M is in state q 0

8 Simulating a multitape TM Single-tape TM: Simulating Multitape TM moves Suppose Multitape TM wants to move like this: q3q3 0/1R ☐ /1R 0/0L q7q7 … 01 01 0 010 … … … 11 01 0 1 010 … … We simulate move on single-tape TM like this: 01010##0#10  # 01010##0#10  #

9 Simulating a multitape TM S:S: On input w 1...w n : Replace tape contents by #w 1 w 2...w n # ☐ # ☐ #    1. To simulate a step of M : 2. qiqi x/x’A y/y’B z/z’C qjqj Remember (in state) that M is in state q 0 #x 1 x 2...x...x i #y 1 y 2...y...y j #z 1 z 2...z...z k #   Make a pass over tape to find x, y, z   If M is in state q i and has transition update state / tape accordingly. If M reaches accept (reject) state, accept (reject). 3.

10 Doing simulations To simulate a model M by another model N : 1. Say how the state and storage of N is used to represent the state and storage of M 2. Say what should be initially done to convert the input of N (if anything) 3. Say how each transition of M can be implemented by a sequence of transitions of N

11 CPU 1010 0100 0000 registers R0R0 R1R1 R2R2 R3R3 arithmetic logical unit 0000 PC What does a computer look like? data memory instruction memory

12 What does a computer look like? CPU 0000 1010 0100 0000 registers R0R0 R1R1 R2R2 R3R3 data memory instruction memory arithmetic logical unit PC 0000 load 0001 0001 write R3 0010 store R5 0011 add R5 0100 jpos 0011... 0110 0000000100100011 0110 0100

13 Instruction set load x load R k store R k read R k write R k jump n jpos n Put the value x into R 0 add R k Copy the value of R k into R 0 Copy the value of R 0 into R k Copy the value at memory location R k into R 0 Copy the value of R 0 into memory location R k Add R 0 and R k, and put result in R 0 Set PC to n Set PC to n, if R 0 is positive jzero n Set PC to n, if R 0 is zero

14 Random access machines load -7 R 0 := -7 write R2 M[R 2 ] := R 0 store R1 R 1 := R 0 add R1 R 0 := R 0 + R 5 jzero 3 if R 0 = 0 then PC := 3 accept instructionmeaning 012345012345 0 PC 0 R0R0 0 R1R1 0 R2R2 2 M 1220 0 1234 program counter registers memory … It has registers that can store integer values, a program counter, and a random-access memory

15 Random access machines load 7 R 0 := 7 write R2 M[R 2 ] := R 0 store R1 R 1 := R 0 add R1 R 0 := R 0 + R 1 jzero 3 if R 0 = 0 then PC := 3 accept instructionmeaning 012345012345 0 PC 0 R0R0 0 R1R1 0 R2R2 0 M 0000 0 1234 … 7 -7 7 14 1 2 3 4 5 The instructions are indexed by the program counter Initially, the input is in the first k memory cells, all registers and PC are set to 0

16 Random access machines Simulating a Turing Machine on a RAM: Random access machines are equivalent to Turing Machines PC 2 R0R0 1 M 2100 … M … 211  = {0, 1, 2,..., k} head tape blank

17 Simulating a TM on a RAM 0 1 2 3 6 7 8 9 10 store R1 handle for state q 0 0 store R1 handle for state q 1 … … accept handle for state q acc 30 200 M q0q0 q1q1 1/2R … 211 store R1 save head position read R1 read tape contents x add -1 jzero 6 if x = 1 goto line 6 load 2 new value of cell write R1 write in memory load R1 recall head position add 1 move head to right jump 30 go to state q 1 program 0 PC 0 R0R0 1 M 21 0 R1R1

18 Simulating a TM on a RAM 0 1 2 3 6 7 8 9 10 store R1 handle for state q 0 0 store R1 handle for state q 1 … 30 M q0q0 q1q1 1/2R … 211 2 R0R0 1 M 21 store R1 save head position read R1 read tape contents x add -1 jzero 6 if x = 1 goto line 6 load 2 new value of cell write R1 write in memory load R1 recall head position add 1 move head to right jump 30 go to state q 1 program 0 R1R1 1 0 2 2 2 3 (head) (tape) … 2

19 Simulating a RAM on a Turing Machine The configuration of a RAM consists of –Program counter –Contents of registers –Indices and contents of all nonempty memory cells 14 PC 3 R0R0 17 R1R1 5 R2R2 2 M 0120 1234 … configuration = (14, 3, 17, 5, (0, 2), (2, 1), (3, 2)) 0

20 Simulating a RAM on a 2-tape TM The TM has a simulation tape and a scratch tape The simulation tape stores RAM configuration The TM has a set of states corresponding to each program instruction of the RAM The TM tape is updates according to RAM instruction (14,3,17,5,(0,2),(2,1),(3,2)) M

21 Simulating a RAM on a 2-tape TM Initialization S:S: On input w 1...w n : Replace tape contents by (0, 0, 0,..., 0, (0, w 1 ), (1, w 2 ),..., (n-1, w n )) 1. TM input: RAM initial state: 0 PC 0 R0R0 1 M 22 122 0...

22 Simulating a RAM on a 2-tape TM Example: load R1 (14,3,17,5,(0,2),(2,1),(3,2)) 2. Write R 1 to conf tape c 1. Copy R 1 to scratch tape 17 s (14,1,17,5,(0,2),(2,1),(3,2)) 17 c s (14,1,17,5,(0,2),(2,1),(3,2) ) c c.. Make more space as needed (14,17,17,5,(0,2),(2,1),(3,2)) c 3. Erase scratch tape 4. Update PC (15,17,17,5,(0,2),(2,1),(3,2)) c

23 Simulating a RAM on a 2-tape TM S:S: On input w 1...w n : Replace tape contents by (0, 0, 0,..., 0, (0, w 1 ), (1, w 2 ),..., (n-1, w n )) 1. 2. Simulate instruction in RAM program by a sequence of TM transitions See notes for details. 3. If RAM instruction is accept, go to accept state. If RAM instruction is reject, go to reject state.


Download ppt "CSCI 3130: Automata theory and formal languages Andrej Bogdanov The Chinese University of Hong Kong Variants."

Similar presentations


Ads by Google