REALIZATION-INDEPENDENT TESTING OF DIGITAL SYSTEMS R. Šeinauskas Kaunas University of Technology LITHUANIA.

REALIZATION-INDEPENDENT TESTING OF DIGITAL SYSTEMS R. Šeinauskas Kaunas University of Technology LITHUANIA

Outline n n Introduction n n Design flow n n The influence of circuit re-synthesising on the fault coverage n Universal test sets n High-level fault models n Test Generation Capabilities for the Black-Box model for the Black-Box model n n Conclusions

Introduction Idea, Algorithm RTL Description Gate Level Netlist Layout Defect-Based Test Generation Defects Conventional Test Generation Fault model of gates High-Level Test Generation Description distortion model Test Generation for Algorithms Black-box fault model

Test Generation Tasks Conventional Test Generation Fault model of gates High-Level Test Generation Description distortion model Test Generation for Algorithms Black-box fault model Defect-Based Test Generation Defects Test generation for all possible realizations of circuit description Test generation for defects Test generation for all possible realizations of cells Test generation for all possible descriptions and all possible realizations of circuit

ASIC Design Flow n n In the standard ASIC design flow the designers mainly work on RT- (or higher) level descriptions. n n Nowadays logic synthesis tools automatically generate gate-level descriptions. n n However, most of the test activities (test structure insertion, test vector generation, fault coverage evaluation, etc,) are still performed on the gate- level netlists.

Drawbacks n n This situation has several drawbacks: n n the design testability is known only after the analysis of the gate-level netlist n n the design changes for testability have to be done back on the RT-level description n n re-synthesizing and re-validating increases design time and reduces quality n n test generation is performed on very large netlists which do not include high-level functional information

Time-to-Market n n Time-to-Market depends on the duration of the logic and layout synthesis and on the duration of the design for test and test generation. n n The design for test and test generation on the system level-level model can reduce time-to- market. n n Starting test development at the end of the design process greatly prolongs the time-to-market.

System-level model n n If a top-down design methodology is used, then a system-level model of the chip exists early in the design process. n n This system-level model can be used during the development of the test program. n n Thus, the test engineers can become involved with the project much earlier, and like the block designers, are given a working virtual prototype of the chip in the form of a system–level model.

Time-to-Market System- level model RT-level model Gate-level model Layout DFT and Test generation

Design complexity n n Design complexity drives the need to reuse legacy or IP ( intellectual Property) cores in Systems on a chip ( SoC). n n High Level modules of SoC are often specified in terms of their behavior only. n n SoC designs rely heavily on reusable and pre- designed cores or intellectual property ( IP) modules, whose gate-level implementation details are unavailable.

Test reuse n n Systems designers become system architects reusing more and more proven components and their test processes. n n Test reuse must follow the same path. n n Conventional single–at fault models associated with internal logical gates or their inter connections are not applicable for test reuse. n n Structural defect-based test involves no test reuse, as tests are usually generated after structural synthesis.

Reusable tests n n The implementation depends on SoC manufacturing technologies and is permanently changing in SoC lifecycle. n n Time-to-Market, reuse legacy or IP cores in Systems on a chip design drives the need to use realization-independent testing. n n How core vendors can provide reusable tests for new implementations?

Important questions n n Can a test based on functional fault model be effective in uncovering physical defects? n n How is its effectiveness dependent on the synthesized structure? n n These are important questions, not only for test reuse, but also due to fact that soft cores can be synthesized by different electronic design automation systems, and mapped in different cell libraries and manufacturing technologies.

Realization-independent testing n n Test generation on system-level model cannot guarantee the complete fault coverage on gate-level model for each possible realization n n Time-to Market depends on ASIC design flow process.

Design Flow System- level model Gate-level model Synthesis DFT and Test generation Time-To-Market System- level model Synthesis DFT and Test generation Gate-level model Test sequences Test supplement on switch-level model Test supplement on System-level model Defect coverage analysis

Design Flow n n In any case fault coverage analysis on gate level model is necessary, but it is not time consuming task. n n The length of test sequences generated on system- level model can be compacted together with the fault coverage analysis. Therefore, the length of test sequences generated on system-level model is not a critical parameter.

The influence of circuit re-synthesising on the fault coverage n n The core can be synthesized by different electronic design automation systems, and mapped in different cell libraries and manufacturing technologies. n n An important issue is how the test set of the core covers the faults of new implementations, which are done by the same synthesizer. n n The experiments have been done with ISCAS’85 benchmarks.

Three realizations n n The original ISCAS’85 circuits have been re- synthesized with Synopsys Design Compiler program by default mode and by using AND-NOT cell library of two inputs. n n The test sets have been generated for each original ISCAS’85 circuit and for each re- synthesized circuit by deterministic algorithm and by random plus deterministic algorithm. n n The fault coverage of each test set for each circuit realization was computed

Three Realizations CircuitsNon redundant ISCAS’85 circuitsSynopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size# of Stuck-at faults Test Size# of Stuck-at faults Test Size# of Stuck-at faults C432635074742650460 C4996375078978901246 C880549425185754928 C135592156610016161101406 C1908123186260876811224 C2670113199012015001141658 C3540172312614424741432520 C53151305248923879974130 C6288347638496680397498 C7552209703915445781364798

Test size of realizations

Three realizations

Deterministic test patterns (Synopsys ATPG ) CircuitsNon redundant ISCAS’85 circuits Synopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size #Stuck- at faults of two other realizatio n Undetect ed faults of two other realizatio n Test Size #Stuck- at faults of two other realizatio n Undetect ed faults of two other realizatio n Test Size #Stuck- at faults of two other realizatio n Undetect ed faults of two other realizatio n C432638861147967295093325 C4996322241607819962890172824 C88054178505118703654179920 C135592271245100297218110288224 C190812321004603086199812738141 C2670113315865120364832114349025 C3540172499412144564665143560059 C53151308009209293788297912794 C6288341417857491513627391431821 C75522099376411541183720613611617285 Total1053494224158955653672291454232718 Percent 0,84% 1,28% 1,32%

Undetected faults of two other realizations

CircuitsNon redundant ISCAS’85 circuitsSynopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size #Stuck-at faults of two other realization Undetected faults of two other realization Test Size #Stuck-at faults of two other realization Undetected faults of two other realization C43257886546967204593318 C499542224827419962080172824 C88062178514918701750179918 C135586271201002972880288224 C190811821002573086212752738131 C2670105315879120364830116349035 C3540167499410143564669147560060 C531513080092099937882899127121 C6288431417810047151369341431828 C75522119376251461183723913811617273 Total1033494223248815653670685454232732 PercentMax. –3,68%0,66%Max. –6,86%1,25%Max. –4,78%1,35% Random plus deterministic test patterns (Synopsys ATPG)

CircuitsNon redundant ISCAS’85 circuitsSynopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization C43212088629396710959339 C4999022244911719961015217286 C880116178501001870510417999 C1355178271201832972419028828 C1908241210021173086130156273880 C267021831582724036481723034907 C354033949943287564624290560020 C531526080091191937824186912730 C6288771417849615136073143182 C7552420937643001183714227411617147 Total20594942292172456536366175054232318 PercentMax. –2,20%0,19%Max. –4,21%0,65%Max. –2,92%0,59% Merged two sets

Percent of undetected faults

All possible realizations Universal test sets All possible realizations

Universal test sets Realization-independent testing is based on the concept of a universal test set. n n The testability properties of different forms of two-level AND-EXOR networks have attracted many researchers.

Realization-Independent Tests n n The size of the universal test sets is small for functions that are fully unate, but it becomes exhaustive for binate functions. n n In general, it exploits the unateness property of a module’s variables, and is composed of functionally defined minimal true and maximal false tests. n n A universal test set can detect both single and multiple stuck-at faults in realizations with restrictions on their structure.

Unate-gate networks n n It has been proved that the universal test set detects all MSL faults in a realization R under the following restriction: n n every path between two points in R (excluding the stems of primary inputs) has the same inversion parity; n n these realizations are called unate-gate networks

Balanced inversion parity ( BIP) network n n The unate-gate restriction is strict and practically it is often replaced by relaxed condition. n n Realization R of function is a balanced inversion parity ( BIP) network, if paths from unate variables have same inversion parity. n n BIP realizations allow paths with different inversion parities between any binate variable and the outputs of a network, and so apply to any practical realization.

BIP realization n n It has been shown recently that in the worst case unate-gate networks are at most twice as large as the minimal implementation. n n BIP realizations, on the other hand, tend to be minimal or near-minimal.. Any BIP realization can be obtained from a unate- gate network by applying a set of resubstitution and De Morgan transformation.

The size of the universal test set n n Universal test set detects all detectable multi stuck-at faults in BIP realization. n n The size of the universal test set for a unate function is relatively small, but for a binate function equals the size of exhaustive test. n n The exhaustive test (2 n ) includes all possible test vectors of n inputs.

Complete test set n n In general case it is impossible to get a complete test set less than the exhaustive test without information about concrete realization of the module. The complete test detects all single stuck-at faults of the module described in terms of primitive gates.

A cell fault n n A cell fault implicitly models all defects that alter a module’s truth table and so provides a high degree of realization independence. n n However, this model can only be applied to very small modules, because often it requires an exhaustive test set comprising all possible input vectors.

The input pattern fault model n n The input pattern fault model uses a true table of function as well. n n Each input pattern fault defines an input and output pattern pair and corresponds the faulty behavior of module. n n The number of faults for even small modules is large.

The coupling faults n n The coupling faults can alter output values in response to changes occurring on one or more inputs of a function n n The simplest case is a single coupling fault, which is defined in terms of a single input/output signal pair. n n The coupling test sets share some properties with universal test sets, but are not necessarily exhaustive for binate functions. n n The coupling test sets are enough large even for small functions

Higher-level fault models n n Higher-level fault models have been proposed for realization-independent functional testing of combinational circuits. n n Logic/arithmetic operations, constant/ variable switch, null statements, if/else, case, for instructions considered as RTL fault models. n n In some cases, their effectiveness in covering stuck-at faults on the circuit’s structural description has been ascertained. However, this does not guarantee their effectiveness to uncover physical defects or stuck-at faults.

The high-level fault models n n The high-level fault models taken from software testing have three main advantages: they are well known and quite standardized; they require little calculations, apart from the complete fault-free simulation; and they are already embedded in some commercial tools. n n However, while such metrics may be useful to validate the correctness of a design, they are usually inadequate to foresee the gate-level fault coverage with high degree of accuracy.

Other approaches n n Some approaches rely on a direct examination of the HDL description or exploit the knowledge of the gate-level implementation. Some extract of the corresponding control machine from a behavioural description is used. n n The listed approaches are of limited generality and the adequacy of testing defects or of the coverage stuck-at faults on the gate level are not proved.

Black-box view n n The behavioral view or “black-box” represents the system by defining the behavior of its outputs according to values applied on its inputs without knowledge of its internal organization. n n In this case only the input-output connectivity can be fixed. The connectivity fault models are rough enough compared to the stuck at fault model. However, the experimental investigation of fault models based on input-output paths testing demonstrated high defect and stuck-at fault coverage on the benchmark circuits.

The n –detection test sets n n An n –detection test set is one where each modeled fault is detected either by n different tests, or by the maximum number of different tests that can detect the fault if this number is smaller than n.. In various types of experiments reported, n detection test sets were shown to be useful in achieving high defect coverage for all types of circuits and for different fault models.

The Pin Pair fault model n n Let the circuit have a set of inputs X = {x 1, x 2,...,x i,...,x n } and a set of outputs Y = {y 1, y 2,...,y j,...,y m }. n n The pin fault model considers the stuck-at- 0/1 faults occurring at the module boundary n n Input-output pin stuck-at fault pairs (x i t, z j k ), t=0,1, k=0,1 are called pin pair faults (PP).

Testing of the PP fault n n The test vector detects the pin pair fault (x i t, z j k ) of the module if the test vector detects both the pin faults x i t, and z j k of the pair on the output z j of the module. n n The PP fault (x i t, z j k ) of a module is testable if a conventional deterministic test generator for a realization of the module finds a test vector, which detects a pin fault x i t on an output z j while the input x i and the output z j are set up to the ¬t and ¬ k

Demonstration Circuit 01 00 0 1 0 1 0 1

Demonstration 01 11 0 1 1 0 1 0

Fault and Test Sets CircuitsStuck-at Faults Test sizeConnectivity Faults Test size C43250763540122 C4997506351841053 C880942541326379 C135515669251841023 C190818621233004620 C267019901133320461 C354031261722588513 C53155248130105401113 C62887638343068246 C75527039209121881681

Stuck-at Fault Coverage CircuitUndetected of R1 Undetected of R2 Undetected of R3 C43211 (2,2%)6 (1,4)%3 (0,7%) C499000 C880000 C1355001 C190864 (3,4%)9 (1.0%)9 (0,7%) C26708 (0,4%)7 (0,5%)6 (0,4%) C354035 (1,1%)25 (1,0%)30 (1,2%) C5315000 C6288000 C755225 (0,4%)8 (0,2%)4 (0,1%) Total143 (0,5%)55 (0,2%)53 (0,2%) R1 – The non-redundant ISCAS’85 benchmark circuit R2 – Synopsys Design Optimization, the target library – class.db R3 - Synopsys Design Optimization, the target library – and_or.db

PP Fault Coverage CircuitsConnectivity Faults Deterministic testsRandom+deterministic tests DetectedPercentDetectedPercent C43254040675,1346786,48 C4995184151029,13143427,66 C880132683763,1286265,01 C13555184271852,43263850,89 C19083004152150,63174057,92 C26703320220466,38214264,51 C35402588205179,31203678,73 C531510540714867,88730569,30 C62883068235376,74239377,99 C755210262 Total450162074859,692101760,47

CircuitsNon redundant ISCAS’85 circuitsSynopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization C43212288671229672612293321 C499105322240105319960105317280 C880379178503791870137917991 C1355102327121102329721102328820 C1908620210012620308657620273859 C267046131588461364814461349010 C3540513499439513564665513560050 C5315111380090111393780111391270 C6288246141780246151360246143180 C75521728937639172811837111172811617108 Total725849422106725856536275725854232249 PercentMax. –0,78%0,21%Max. –2,69%0,49%Max. –2,25%0,46% Black-box test connections tested at least once

CircuitsNon redundant ISCAS’85 circuitsSynopsys Design Optimization- class.db Synopsys Design Optimization- and_or.db Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization Test Size#Stuck-at faults of two other realization Undetected faults of two other realization C432468886046896744689334 C499622122240622119960622117280 C880138117850138118700138117990 C1355618627120618629720618628820 C190829682100629683086162968273818 C2670192231582192236482192234904 C3540199749941119975646161997560013 C5315550780090550793780550791270 C6288126214178012621513601262143180 C755250049376265004118377450041161776 Total32916494224532916565361123291654232115 PercentMax. –0,28%0,09%Max. –0,63%0,20%Max. –0,66%0,21% Black-box test connections tested at least twice

Percent of undetected faults

Maximum and on average percent of undetected faults Maximum percent of undetected faults On average percent of undetected faults One test set 7,191,12 Two test sets 4,210,48 Test set for testing of connections 2,69 0,39 Test set for twice testing of connections 0,660,17

Flowchart System- level model Gate-level model Synthesis DFT and Test generation Time-To-Market System- level model Synthesis DFT and Test generation Gate-level model Test sequences Test supplement on switch-level model Test supplement on System-level model Defect coverage analysis

Test set compaction n n Test sets could be compacted according to the defects of circuits only n n The length of test sequences generated on system-level model is not a critical parameter, because it can be easily reduced by fault coverage analysis on the gate-level or switch-level models

Software testing n n Connectivity testing is applicable for software testing as well n n Software runs on some hardware indeed n n The question is open how connectivity tests detect software faults

Test generation for algorithms n n The simplest approach for black-box test generation is selection test vectors from random generated according to the connectivity criteria. n n The random search can be stopped if fixed amount of generated vectors did not detect new connectivity between input and output

Test generation procedure n n Each input vector has sensitive inputs, which value change impact the outputs n n The input vectors adjacent to the sensitive inputs have to be evaluated n n The evaluated input vectors have new adjacent input vectors of sensitive inputs and so on.

Test generation procedure n n The procedure continues until no vector have been selected from the new set of adjacent input vectors n n The new random input vector will be generated for repeated search in this case n n The procedure terminates due to low efficiency of search

Example 0000 1111 1000 1100 0100 0011 0001 0010 11101101 1010 0101 1011 01110110 1001

Tools on the internet n http://www.elen.ktu.lt/etg/results.html http://www.elen.ktu.lt/etg/results.html n Online test synthesis tool. Interface through browser n Black-box model on C n Registration, password

Conclusions n n Test of black-box are realization independent and can be reused by software and hardware implementations of algorithm. n n Re-synthesizing of circuit with different target libraries and test reuse can not detect about one percent of stuck-at faults.

Conclusions n n The design for test and test generation on system-level model reduces time-to- market n n Test generation on system-level model can not guarantee the complete fault coverage on gate-level model for each possible implementation

Conclusions n n Test generation on system-level model is preferable if the efforts and duration of test supplement activities are less than the efforts and duration of test generation on gate-level model. n n Black-box fault models ensure fault detection on gate-level model like two- detection test for re-synthesized circuit with different target libraries

REALIZATION-INDEPENDENT TESTING OF DIGITAL SYSTEMS R. Šeinauskas Kaunas University of Technology LITHUANIA.

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REALIZATION-INDEPENDENT TESTING OF DIGITAL SYSTEMS R. Šeinauskas Kaunas University of Technology LITHUANIA.

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