1. INTERPRETATION OF THE SINGLE EVENT UPSET IN STATIC RANDOM ACCESS MEMORY CHIPS INDUCED BY LOW ENERGY NEUTRONS B. Mukherjee 1, D. Makowski 2 M. Grecki 2, S. Simrock 1 1 Deutsches Elektronen Synchrotron, Hamburg, Germany 2 Department of Microelectronics and Computer Science, TUL, Poland 12 th International MIXDES Conference, 22-25 June 2005, Krakow, Poland

2. INTRODUCTION Microelectronic devices operating in the radiation environment of high-energy particle accelerators are prone to radiation induced malfunctions. In particular, the unprecedented, recoverable, short-term failure of the electronic instrumentation and control systems triggered by Single Event Effect (SEE) causes great concern. The SEE is initiated by short excursion of radiation level, particularly due to neutrons, usually occurs during an unforeseen beam loss event at high-energy accelerators. The interaction of densely ionising (high LET) secondary particles produced via the neutron induced nuclear reaction within the microchip sets off the SEE. In this presentation the SEE induction mechanisms of isotopic ( 241 Am-Be) as well as accelerator produced neutrons in various types SRAM chips are highlighted.

3. MECHANISM OF TRIGGERING A SEU In a microelectronic circuit (M), embedded in the semiconductor substrate (S) a Single Event Upset (SEU) set off when the interacting ionising particle deposits sufficient energy in the sensitive volume enclosing the critical node (N). The SEU triggering mechanism could be divided in two broad categories: (a) Direct Interaction The high energy heavy (HZE) particle, i.e. of cosmic origin (P) directly interact with the critical node (N) by producing a track of electron/hole pairs, thereby causing the SEU. (b) Indirect Interaction The primary particle, i.e. accelerator produced neutron undergo nuclear reaction with the primary atom (A) producing primary knockout atom (PKA) and secondary charged particle (CP), producing the SEU.

4. PHYSICAL PHENOMENA GOVERNING THE SEU The impinging particle deposits the energy (E d ) along the track length (s) within the semiconductor substrate of density (  ): E d = L. .s (1) where, L = LET of the impinging particle in the semiconductor material The electric charged (Q d ) required to create an electron/hole pair in the semiconductor material: Q d = E d.q / w ehp (2) where, q = elementary charge, 1.602 x 10 -19 Coulomb and w ehp = energy (eV) required for the production of one electron/hole pair The minimum (threshold) LET (L th ) required to create an SEU: L th = (Q crit.w ehp ) / (q. .s max )(3) where, Q crit = minimum electric charge required to create an electron/hole pair, s max = maximum track length of the impinging particles of a given LET in the semiconductor material

5. PHYSICAL PHENOMENA GOVERNING THE SEU (contd.) The minimum track length (s min ) of the impinging particle required to create an SEU: s min = (Q crit.w ehp ) / (q. .L)(4) where, L = LET of the impinging particle in the semiconductor material In case of neutrons, the critical charge (Q crit ) depends on the energy spectra. The Q crit of fission neutrons (similar to electron linac produced Giant-Dipole-Resonance spectrum) was calculated to be 0.15 pico Coulomb. The physical properties of some important semiconductor materials are shown in the Table below: Using equations 1- 4 one can calculate the number SEU induced in a SRAM.

6. NEUTRON INDUCED NUCLEAR REACTIONS IN THE MICROCHIP Nuclear Reaction with Boron (1) Boron is used as a dopant and component of the glassification layer: 10 B 5 + 0 n 1 = 7 Li 3 + 4 He 2 (1) (Q = + 2.65 MeV) Nuclear Reactions with Silicon (2 & 3) Silicon is the major building block of all semiconductor devices: 28 Si 14 + 0 n 1 = 25 Mg 12 + 4 He 2 (2) (Q = - 2.65 MeV) 28 Si 14 + 0 n 1 = 28 Al 13 + 1 H 1 (3) Q = - 3.85 MeV)

7. NEUTRON INDUCED NUCLEAR REACTIONS IN THE MICROCHIP (contd.) Boron-10 ( 10 B 5 ) makes only 19.9% abundance in natural boron. However, due to very high “exothermic” reaction cross section of 3000 barn for thermal neutrons, the neutron capture reaction (1) overwhelms the “endothermic” (n,  ) and (n, p) reactions (2 and 3) in Silicon (cross sections ca. 0.1 barn). The physical properties of the reaction products of 10 B(n,  ) 7 Li reaction are summarised in Table below. Evidently, due to a higher range (5 micron) in silicon, the alpha particles ( 4 He) are the main candidate for triggering SEU in the microchip.

8. NEUTRON IRRADIATION OF SRAM CHIPS (1) 241 Am-Be Neutron Irradiation Device B: Thermal Neutron Shield (Borated Polyethylene) D: Device under Test (DUT) H: Table J1, J2: Jars (16 and 33 cm radius respectively) P: Stand S: 241 Am-Be Neutron source T: Tripod (Source holder) 512 kB non-volatile SRAM chips were irradiated with 241 Am-Be neutrons and stray neutrons existing in the TTF 2 tunnel. (2) In the TTF 2 (Electron Linac) Tunnel, warm side C: Cable Duct E: Electronic Instrument Cabinet Q: Quadrupole Lens S: SRAM Chips W: Catwalk

9. INTERPRETATION OF EXPERIMENTAL RESULTS The number of SEU counted after neutron irradiation of the 512 kB SRAM chips are shown in the Table below: The normalised SEU counts of the bare, polyethylene- moderated and shielded with Borated Polyethylene (Poly- Bor) sheet are shown in the next Figure. The lowest number SEU in the Poly-Bor shielded SRAM chips irradiated at the Linac reveals the existence of a high number of thermal neutrons in the tunnel.

10. SUMMARY AND CONCLUSION Using the physical principle of nuclear reaction we have analysed the phenomena of Single Event Upset in Static Random Access Memories (SRAM) set off by neutrons. We have investigated the SEU initiated in 512 kB SRAM chips by isotopic neutrons from an 241 Am-Be source as well as stray photo- neutrons produced by the 450 MeV superconducting electron linac (TTF 2 of DESY) and interpreted the results. In the TTF2 tunnel the thermal neutron produced by multiple collision of primary (GDR) Photoneutrons with the containment wall found to be the main source of triggering the SEU. The implementation of a 3.5 mm thick borated polyethylene shield reduced incidence rate of SEU by more than one order of magnitude The main aim of this investigation is to establish an optimum mitigation strategy for the reduction of SEU in SRAM and FPGA chips to be used in the VUV FEL and XFEL facilities of DESY. THANK YOU FOR YOUR ATTENTION (bhaskar.mukherjee@desy.de)