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© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp 92 Parity Method Pp 94 The parity method.

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Presentation on theme: "© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp 92 Parity Method Pp 94 The parity method."— Presentation transcript:

1 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp 92 Parity Method Pp 94 The parity method is a method of error detection for simple transmission errors involving one bit (or an odd number of bits). A parity bit is an “extra” bit attached to a group of bits to force the number of 1’s to be either even (even parity) or odd (odd parity). The ASCII character for “a” is 1100001 and for “A” is 1000001. What is the correct bit to append to make both of these have odd parity? The ASCII “a” has an odd number of bits that are equal to 1; therefore the parity bit is 0. The ASCII “A” has an even number of bits that are equal to 1; therefore the parity bit is 1.

2 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed PP125 Fig 25 A simplified intrusion detection system using an OR gat e.

3 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp128 Fig.30 Standard symbols representing the two equivalent operations of a NAND gate.

4 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp128 Fig 31

5 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp 129 Fig32

6 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp129 Fig 33

7 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp 132 Fig 38 Standard symbols representing the two equivalent operations of a NOR gate.

8 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp133 Fig 40

9 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp134 Fig41

10 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 5. The symbol is for a(n) a. OR gate b. AND gate c. NOR gate d. XOR gate A B X

11 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 6. A logic gate that produces a HIGH output only when all of its inputs are HIGH is a(n) a. OR gate b. AND gate c. NOR gate d. NAND gate

12 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 7. The expression X = A + B means a. A OR B b. A AND B c. A XOR B d. A XNOR B

13 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 8. A 2-input gate produces the output shown. (X represents the output.) This is a(n) a. OR gate b. AND gate c. NOR gate d. NAND gate A X B

14 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 9. A 2-input gate produces a HIGH output only when the inputs agree. This type of gate is a(n) a. OR gate b. AND gate c. NOR gate d. XNOR gate

15 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed © 2008 Pearson Education 10. The required logic for a PLD can be specified in an Hardware Description Language by a. text entry b. schematic entry c. state diagrams d. all of the above

16 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed P131 脈波操作 3-9 pp127/ 中 pp131 若圖 3-28 所示的 A 和 B 兩波輸入 NAND 閘,則輸出波形為何? 解:在時序圖中,共有 4 個時間區間 A 和 B 輸入波皆為 HIGH ,只在 這 4 個時間區段中的輸出波 X 為 LOW 。 相關問題 若 B 輸入波 LOW ,則輸出波和時序圖會有何變化?請畫 出來。 圖 3-28

17 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed P134 脈波操作 例 3-12 ( 續 ) 要注意的是,此例題與例題 3-13 中所使用的是相同的 2 輸 入端 NAND 閘,但電路圖中卻用了不同的符號,這是為了表示 NAND 閘和輸入反相的 OR 閘用法不同。 相關問題 圖 3-32 的電路要如何改良才能監控四個儲存槽內的 液體體積? Pp129/ 中 pp134 圖 3-32

18 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed P144 脈波操作 Pp133 Fig 3-47 若 B 輸入波恒為 LOW ,則 輸出波形和時序圖會 變成怎樣?請畫出來 若 B 輸入波恒為 High?

19 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed P097 以同位法檢測錯誤 表 2-10 由表 2-10 列出每個 BCD 數 要形成偶或奇同位所須的同位 位元,可以看出在數碼上附加 同位位元的方法。各個 BCD 數 的同位位元列在標示 P 的欄中。 同位位元可以附加在代碼 的開頭或末端,端視系統的設 計而定。注意 1 的總數 ( 包含 同位位元在內 ) 在偶同位時要 恆為偶數,在奇同位時則要恆 為奇數。

20 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed P098 以同位法檢測錯誤 2-34 對下列各位元組指定一個適當的偶數同位位元: (a)1010(b)111000(c)101101 (d)100011100101(e)101101011111 解:視情形在各代碼中加入同位位元 1 或 0 ,使整個代 碼中 1 的個數為偶數。同位位元在最左邊。 (a)01010(b)1111000(c)0101101 (d)0100011100101(e)1101101011111 相關問題 在代表字母 K 的 7 位元 ASCII 碼加入一個奇 同位位元。

21 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp180 In Boolean algebra, multiplication is equivalent to the AND operation. The product of literals forms a product term. The product term will be 1 only if all of the literals are 1. Boolean Multiplication What are the values of the A, B and C if the product term of A. B. C = 1? Each literal must = 1; therefore A = 1, B = 0 and C = 0.

22 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Commutative Laws In terms of the result, the order in which variables are ORed makes no difference. The commutative laws are applied to addition and multiplication. For addition, the commutative law states A + B = B + A In terms of the result, the order in which variables are ANDed makes no difference. For multiplication, the commutative law states AB = BA

23 Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 4.1 Application of commutative law of addition. Pp181

24 Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 4.2 Application of commutative law of multiplication.

25 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Associative Laws When ORing more than two variables, the result is the same regardless of the grouping of the variables. The associative laws are also applied to addition and multiplication. For addition, the associative law states A + (B +C) = (A + B) + C For multiplication, the associative law states When ANDing more than two variables, the result is the same regardless of the grouping of the variables. A(BC) = (AB)C

26 Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 4.3 Application of associative law of addition. Open file F04-03 to verify. Pp181

27 Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 4.4 Application of associative law of multiplication. Open file F04-04 to verify.

28 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Distributive Law The distributive law is the factoring law. A common variable can be factored from an expression just as in ordinary algebra. That is AB + AC = A(B+ C) The distributive law can be illustrated with equivalent circuits: Pp182 AB + ACA(B+ C)

29 Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 4.5 Application of distributive law. Open file F04-05 to verify.

30 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Rules of Boolean Algebra 1. A + 0 = A 2. A + 1 = 1 3. A. 0 = 0 4. A. 1 = 1 5. A + A = A 7. A. A = A 6. A + A = 1 8. A. A = 0 9. A = A = 10. A + AB = A 12. (A + B)(A + C) = A + BC 11. A + AB = A + B Pp182


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