1. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 1 WIPER PDR Stanford, CA February 9-10, 2006 9-10 FEB 06 Thermal Analysis Lindy Ahr Southwest Research Institute (210) 522-3212 lahr@swri.org

2. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 2 9-10 FEB 06 Purpose Spacecraft Electronics must have the highest reliability High Junction Temperatures reduce reliability Electronics Allowable Maximum Junction Temperatures are derated to increase reliability Thermal Analysis is used to keep the Electronic Component Temperatures below the derated temperature

3. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 3 9-10 FEB 06 Requirements Compliance MatrixRequirement CRD Rev - C Status All equipment with circuit boards and soldered components shall be designed so that during normal operation, each cards component junction temperature shall be less than 105 degrees Celsius. Exceptions shall be identified and issued a waiver, if appropriate, by the DSX PMO. 4-25.1TBD Unless specifically approved, all electronic parts shall be rated for an operating range of -44 to 61 ºC (-55 to 71 ºC for qualification). 5-15TBD The environment parameters listed in Table IX (Solar Incident Radiation) shall be used for all thermal analysis. 5-14 Not Applicable to Internally mounted Subsystem All computer models and analysis shall be provided to the DSX PMO at PDR. This includes, but is not limited to Spacecraft and payload structural, thermal, and radiation models and analysis results. 7-7Compliant.

4. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 4 9-10 FEB 06 Thermal Assumptions Chassis dissipates waste heat through conduction via mounting flanges to spacecraft. Heat transfer from each electronic module into the housing is through the card guides in the form of conduction Individual components with 50 milliwatts, or greater power dissipation, are explicitly modeled with the remainder of the power from components being averaged across the board Component conduction is via thermal epoxy for surface mount IC’s, solder connections for surface mount leadless devices and pins for through-hole devices that do not receive epoxy or other thermal treatment All circuit boards have dedicated thermal planes of 4 ounces of copper in addition to power and ground planes Power dissipation on boards is taken as nominal expected for all boards. This assumes that worst case dissipations for the entire assembly would not exceed this condition.

5. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 5 9-10 FEB 06 Steady-State Analysis Approach  TAK 2000 finite difference software used to model the enclosure.  Power from modules are used as heat sources at the respective nodes in the enclosure model.  Steady-state temperature profile of the housing was determined and used as boundary conditions on the card models.  Electronics modeling package in TAK 2000, PC Analyze, was used to construct card models.  Card models are comprised of parallel conductors representing the board substrate and the thermal plane, and conductors representing the edge guides.  An equivalent conductance for the board-card guide-wedge clamp-housing thermal path was determined and input into the PC Build models.

6. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 6 9-10 FEB 06 Power Dissipation for Electronics Modules Module Typical Expected Maximum Dissipated Power, Watts POW5.0 CPU4.3 DIG3.0 ANA3.0 NOTES: 1) Assembly analysis is performed with typical expected power dissipations for all modules.

7. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 7 9-10 FEB 06 Thermal Network Diagram of TCU Chassis

8. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 8 9-10 FEB 06 Steady State Temperature of the Chassis NodesModuleMaximum Flight Temp., °C 15/25ANA41.5 13/23DIG41.3 12/22CPU41.0 11/21POW40.6 91TCU Interface Temp.40.0 99Radiation BoundaryNot used

9. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 9 9-10 FEB 06 POW Steady State Board Temperature

10. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 10 9-10 FEB 06 CPU Steady State Board Temperature

11. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 11 9-10 FEB 06 CPU Component Temperatures

12. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 12 9-10 FEB 06 DIG Steady State Board Temperature

13. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 13 9-10 FEB 06 ANA Steady State Board Temperature

14. For Official Use Only; Information herein NOT Approved for Export; Contains Proprietary Protected Information; NOT for Public Release 14 9-10 FEB 06 Summary Insufficient information to accurately model the POW, DIG and ANA Card Modules. Board with uniformly distributed power were modeled. Board Temperatures were plotted. CPU Card Module Results indicate that all analyzed device temperatures meet derating guidelines for junction temperatures for the Flight Hot Temperature Case.