1. Victor Zhirnov April 10, 2011 Potsdam, Germany ERD Memory Discussion

2. ERD Memory Tasks u Update Memory Tables and Text v Implement the decisions made at the 2010 ERD FFM as well as at the 2010 workshops in Barza and Tsukuba n Status: work in progress n 1 st draft (tables): April 2011 n Final draft (tables + text): July 1, 2011 u Create new section on Storage Class Memory v Status: 1 st draft completed v Final draft: April 2011 u Create new section on Select Device v Status: 1 st draft completed v A fundamental study is underway develop an analysis of nanoscale selector devices for memory v Final draft: July 1, 2011 v Research paper: November 2011 2

3. Decisions for Memory Section (Dec. 2 & 5, 2010 ERD Meetings) 3 Action Items for Memory (Dec. 2 & 5, 2010, ERD Meetings) 1. Should Storage Class Memory drive a new architecture discussion in the Architecture Section? Explore a definition of SCM Zhirnov and Schechtman 5. Develop a table of Devices mapped onto materiel and their critical property required to demonstrate the key attribute of the device. Bourianoff Garner and Zhirnov 6. Rename the FeFET to include the Fe-barrier device.Zhirnov 8. Change “Nanobridge Cantilever” to just “Nanobridge”Zhirnov Put Vertical MOSFET in the Memory Section Include new section on Storage Class Memory Include new section on Select Device

4. ERD Memory Tables

5. 5

6. 6 2010 Important Events u Emerging Research Memory Devices Workshop v Barza, Italy, April 2, 2010 u Emerging Memory Materials workshop v Tsukuba, Japan, November 30, 2010

7. 2009 ERD Memory Table 7 Ferroelectric FET memory Nanomechanical Memory Spin Torque Transfer Memory Nano- thermal Memory Nanoionic Memory Electronic Effects Memory Macromolecular Molecular Memories Memory Storage Mechanism Remnant polarization on a ferroelectric gate dielectric Electrostatically- controlled mechanical switch Magnetization of the ferromagnetic layer Thermo- chemical redox process, 2) Thermal phase transformati ons Ion transport and Multiple mechanisms redox reaction Cell Elements 1T1T1R or 1D1R1T1R 1T1R or 1D1R Device Types FET with FE gate insulator 1) nanobridge/ cantilever Magnetization change by spin transfer torque 1) Fuse/Antifu se Memory 1) cation migration 1) Charge trapping M-I-M (nc)-I-M Bi-stable switch 2) telescoping CNT 2) nanowire PCM 2) anion migration 2) Mott transition 3) Nanoparticle 3) FE barrier effects Redox Memory Mott Memory PIDS

8. Summary : STT RAM – 1 st Place in voting Pros  Well defined physical Model and simulation tool.  Very fast improvement. Many chip level papers on IEDM, VLSI and ISSCC  No control device needed (for apple to apple comp. STT RAM vs. Other ReRAM w/ control device)  CMOS compatible and No HV ease of front end integration.  Extendibility : ~1uA Writing current @ 50ns speed ( 50nm diameter P –MTJ @IEDM2009) Even In plane MTJ can be extendible)  Scalable than PCRAM, Nanothermal and Nano electronic memory w.r.t write speed, endurance(>1E12) and retention.  4F2 possible by vertical tr.(Currently ~21F2, 40nm and chip level)  MTJ can be extended to logic devices as an nonvolatile unit. Cons  MLC operation and stacking is difficult  Very much process dependent : - MgO dielectric Reliability ( subsequent temp. and etching ) - Thermal instability(< 150C), different from single cell results. - Even endurance as low as 1E7(chip level) - Hc shift and stuck at 1 or 0 status. - Variation  All parameters are related each other. Need to decouple(ex. retention, programming current, RA, TMR, endurance, speed), Keeping in mind memory is simple device.) Much better developed technology than other ERD memory entries – time to migrate to PIDS

9. Nanothermal and Nanoionic Resistive Switching Memories: A Summary – 2 nd place u Classification v ‘Nanothermal’ and ‘Nanoinic’ often refer to the same mechanisms of resistive switching v Decision: To merge ‘Nanothermal’ and ‘Nanoionic’ in one category – RedOx Memory u Scaling properties v Based on fundamental physics, Nanothermal/Nanoionic memories may be scalable to 10 nm (and below), capable to fast (~ns) operation u Current Application Prospects v Unclear in the context of existing memory hierarchy v Incomplete understanding of operation mechanisms v Lack of predictive models etc. 9

10. 2009 ERD: Electronic Effect Resistive Switching Memories u Charge trapping induced resistive switching u Resistive switching induced by Mott-transition u Ferroelectric resistive switching v Ferroelectric tunnel junction (FTJ) 10

11. Electronic Effect Resistive Switching Memories: A Summary u Charge trapping induced resistive switching v A non-workable concept v Should not be considered in the future u Resistive switching induced by Mott-transition v Needs to be investigated under benchmark values u Ferroelectric resistive switching v Needs to be investigated under benchmark values v Issues: Retention, endurance fatigue, scalability 11

12. Ferroelectric resistive switching u Interesting concept v Ferroelectric tunnel junction - FTJ u Not really “electronic effects memory” v Operation principle is based on ferroelectric polarization, similar to e.g. FeFET v Same difficult problems as in FeFET n Retention, endurance fatigue, scalability u Much smaller number of research papers compared to other types of ReRAM 12

13. Changes in the 2011 ERD Memory section u To take out the “electronic effect memories” entry from the ERD memory table u The Ferroelectric Tunel Junction memory could be covered along with FeFET as a subcategory v Action Item: A new name for ERD ferroelectric memory entry is needed u Mott Memory will form a stand-alone entry 13

14. Resistive switching induced by Mott-transition: An optimistic view u Very interesting concept (believed by enthusiasts to be the ultimate solution for nanodevices) 14 Silicon-based contemporary electronic devices based on a naive electrostatic charging are reaching their miniaturization limits... Alternative ideas are craved: for example, using phase transitions rather than the charge storage…The ultimate resistance-change device is believed to exploit a purely electronic phase change such as the Mott transition… I. H. Inoue and M. J. Rozenberg,”Taming the Mott Transition for a Novel Mott Transistor”, Adv. Funct. Mater. 2008, 18, 2289–2292

15. Mott memory issues: I- Research Activity u Much smaller number of research papers compared to other types of ReRAM v Most of the papers are theoretical u In experiments, different conductive mechanisms may contribute to the resistive switching v Only a few experimental works presenting evidences for Mott transition 15 R. Fors, S. I. Khartsev, and A. M. Grishin, ‘Giant resistance switching in metal-insulator- manganite junctions: Evidence for Mott transition’, PHYS. REV. B 71, 045305 (2005)

16. Mott memory issues: II – Scaling u Scaling of Mott devices might be a problem v What is the minimum number of atoms in a Mott memory element to provide retention and sensing properties? u Needs to be investigated under benchmark values 16 An Chen: Although switching devices on the scale of 200 nm has been shown to have the characteristics similar to these observed in larger devices, this size is far from being competitive to existing memory technologies. More research on the size effect of the Mott transition properties is needed to address the fundamental scaling limit of this type of devices.

17. 2011 ERD Memory Table 17 Ferroelectric effects memory Nanomechanical Memory Redox Memory Mott Memory Macromolecular Memory Molecular Memories Storage Mechanism Remnant polarization on a ferroelectric gate dielectric Electrostatically- controlled mechanical switch Ion transport and Multiple mechanisms redox reaction Cell Elements 1T or 1T1R1T1R or 1D1R Device Types FET with FE gate insulator FTJ 1) nanobridge/ cantilever 1) cation migration M-I-M (nc)-I-M Bi-stable switch 2) telescoping CNT 2) anion migration Mott transition 3) Nanoparticle

18. Action Item: A new name for ERD ferroelectric memory entry is needed u Combines two subcategories: v Ferroelectric FET v Ferroelectric tunnel junction u Should not be confused with conventional ferroelectric memory or FeRAM v Based on FE capacitor v Is currently in PIDS u Temporary working name: v Ferroelectric effects memory v Suggestions are welcome 18

19. Memory Select Device

20. Memory Select Device TWG: 20 Dirk Wouters (IMEC) Rainer Waser (U Aachen) Thomas Vogelsang (RAMBUS) Zoran Krivokapic(GLOBALFND) Al Fazio (Intel) Kyu Min (Intel) U-In Chung (Samsung) Matthew Marinella (Sandia Labs) Wei Lu (U Michigan) An Chen (GLOBALFND) Kwok Ng (SRC) Victor Zhirnov (SRC) The fundamental study team

21. ReRAM Select Device: TransistorConventional approach Diode Other 2-terminal non-linear element? Enables cell scaling to 4F 2 Supports 3D-stacking Potentially lower cost etc.

22. General remarks on Memory Select Device u The select device is a non-linear element, which can operate as a switch. v Typical examples: transistors (e.g. FET or BJT) or diodes. v Up to now, FET is commonly used as select device in practical memory arrays, such as DRAM or flash. v In order to achieve the highest planar array density of 4F 2, without considerable overheads associated with vertical select FETs, passive memory arrays with two- terminal select device are currently actively investigated where two-terminal devices with switch-type behavior (e.g. diodes) are integrated in series with resistive storage nodes in a cross-bar array. 22

23. Suggested select device categories (An Chen/GF) Select devices Transistor Planar Vertical Diode p-n junction Schottky junction Hetero- junction Switch- based selector Mott transition switch Threshold switch Resistive switch Mixed ionic electronic conduction (MIEC) Complementary resistive switch structure

24. Transistor-type select devices u In order to reach the highest possible 2-D memory density of 4F 2, a vertical select transistor needs to be used v the approach being currently actively pursuit. u While vertical select transistor allows for the highest planar array density, this 4F 2 technology is more difficult to integrate into stacked 3D memory, than the conventional 8F 2 technology using planar FETs v to avoid thermal stress on the memory elements on the existing layers, the processing temperature of the vertical transistor as selection devices in 3D stacks has to be low, which is not available for high-quality transistors). u Also, making contact to the third terminal (gate) of vertical FET constitutes additional integration challenge. 24

25. Decisions for Memory Section (Dec. 2 & 5, 2010 ERD Meetings) 25 Action Items for Memory (Dec. 2 & 5, 2010, ERD Meetings) 1. Should Storage Class Memory drive a new architecture discussion in the Architecture Section? Explore a definition of SCM Zhirnov and Schechtman 5. Develop a table of Devices mapped onto materiel and their critical property required to demonstrate the key attribute of the device. Bourianoff Garner and Zhirnov 6. Rename the FeFET to include the Fe-barrier device.Zhirnov 8. Change “Nanobridge Cantilever” to just “Nanobridge”Zhirnov Put Vertical MOSFET in the Memory Section Include new section on Storage Class Memory Include new section on Select Device OK

26. Two-terminal Select Device u Diode-type select devices v pn-diode, v Schottky diode v and heterojunction diode v Zener or avalanche diodes. u Resistive-Switch-type select devices v innovative device concepts that exhibit resistive switching behavior. v in some of these concepts the device structure/physics of operation is similar to the structure of the storage node. v A modified memory element could act as select device! n a ‘nonvolatile’ switch is required for the storage node, while for select device depending on the approaches non-volatility may not be necessary and can sometimes be detrimental. 26 Unipolar cell Bipolar cell

27. Selection Device Benchmarking u ‘Waser 2010’ (individual cell-based) v V on ~ 1 Volt  I on min ~ 1  A v J on ~10 6 A/cm 2 for L~10 nm u ‘Hwang 2010’ ( cross bar array with a 1-100 Mb block density) v V on ~ 1-5 Volt v J on ~ 10 5 – 10 6 A/cm 2 v ON/OFF > 10 7 -10 8 27 G. H. Kim, K. M. Kim, J. Y. Seok, H. J. Lee, D-Y. Cho, J. H. Han and C. S. Hwang, “A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory”, Nanotechnology 21 (2010) 385202 H. Schroeder, V. V. Zhirnov, R. K. Cavin, and R. Waser, “Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells ”, J. Appl. Phys. 107 (2010) 054517

28. Resistive-Switch-type select devices I u Mott-transition switch v is based on the Mott Metal-Insulator transition v a volatile resistive switch, v A VO 2 -based Mott-transition device has been demonstrated as a selection device for NiO x RRAM element [Ref: M.J. Lee, “Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory,” Adv. Mater. 19, 3919 (2007).]. v The feasibility of the Mott-transition switch as selection devices still needs further research. u Threshold switch v is based the threshold switching in MIM structures caused by electronic charge injection/trapping v Significant resistance reduction can occur at a threshold voltage and this low-resistance state quickly recovers to the original high-resistance state when the applied voltage falls below a holding voltage. 28

29. Resistive-Switch-type select devices II u MIEC switch v observed in materials that conduct both ions and electronic charges – so called mixed ionic electronic conduction materials (MIEC). v The resistive switching mechanism is similar to the ionic memories. u Complementary resistive switch v the memory cell is composed of two identical non-volatile ReRAM switches connected back-to-back. v Example: Pt/GeSe/Cu/GeSe/Pt structure v Electrically, it can be represented by a antiserial connections of two intrinsic Schottky diodes, which are formed at the contact sides of both cells v Can be placed into the category of Diode-type select devices 29

30. 30 Selector typeMaterial System V on1 I on1 V on2 I on2 ON/OFFFREF Unipolar cell pn-diodePoly-Si (E)1 20  A 2×10 4 A/cm 2 --10 5 0.3  m van Duuren 2007 Schottky diode n-ZnO (E)1 45  A 500 A/cm 2 --10 5 3  m Huby 2008 Ge NW (E)1 1  A 500 A/cm 2 --10 2 0.5  m Wong 2008 a-Si (I)1100 nA 1000 A/cm 2 --10 6 100 nmLu 2010 p-Si (E)1 10  A 1000 A/cm 2 --10 3 1  m Lee 2010 Pt/TiO 2 16 mA 10 A/cm 2 --10 9 245  m Hwang 2010 Heterojunction diode n-ZnO/p-Si325 mA 250 A/cm 2 --10 3 100  m Choi 2010 CuO/InZnO1 2.5  A 1000 A/cm 2 --10 3 0.5  m Park 2009 Bipolar cell Zener diode(E)Toda 2009 Reverse breakdown Schottky diode Cu/n-Si1 10  A -3 10  A 10 3 2  m Kozicky 2010 Complementary resistive switch Pt/GeSe/Cu/Ge Se/Pt 1 600  A 2400 A/cm 2 600  A 2400 A/cm 5  m Waser 2010 Diode-type select devices

31. 31 Select DeviceMaterial SystemV on1 I on1 (J on1 ) ON/OFFFREF Mott transition switch Pt/VO 2 /Pt0.4/0.6V (400 A/cm 2 )10 3 Lee 2007 Threshold switch Chalcogenide alloy (undisclosed) 10 6 Kau 2009 MIEC switch~140 nmGopalakrishnan 2010 Complementary resistive switch Pt/GeSe/Cu/GeSe/Pt1 600  A 2400 A/cm 2 5  m Waser 2010 Resistive-Switch-type select devices Source: Philip Wong / Stanford

32. Criteria for the evaluation of selection devices (An Chen/GF) ParametersExplanations Blocking state resistance Measure the resistance from the selection devices in the blocking state; it is generally a voltage-dependent value The higher the blocking state resistance the better Conductive state resistance Measure the resistance from the selection devices in the conductive state; it is generally a voltage-dependent value The smaller the blocking state resistance the better Turn-on voltage The voltage where the selection devices become sufficiently conductive Turn-on speed How fast the selection devices turn on, which affect switching dynamics Turn-off voltage The voltage where the selection devices become nonconductive (high resistance) Turn-off speed How fast the selection devices turn off, which affect switching dynamics Operation polarity Blocking/conductive states exist in both polarities (suitable for bipolar switching devices) or each in different polarity (suitable for unipolar switching devices) Scalability How scalable is the selection devices Linearity Linear or nonlinear I-V characteristics in blocking and conductive states Processing temperature Low processing temperature is preferred Materials What materials are required? How available are they? Are they compatible with the processing of the resistive switching devices? Structures Two terminal or three terminal

33. Scaling limits of two-terminal semiconductor non-linear elements Victor Zhirnov 1, Kwok Ng 1, An Chen 2, Wei Lu 3 1 Semiconductor Research Corporation 2 GlobalFoundaries 3 University of Michigan

34. 2-terminal selector devices u External selecting device OR storage element with inherent rectifying/isolation properties v 2-terminal structure with non-linear characteristics n e.g. switching diode-type behavior for unipolar memory cells n for bipolar cells, selectors with two-way switching behavior are needed, e.g. Zener diode, avalanche diode etc. 34 I V OFF I ON I ON1 ON 1 ON 2 OFF unipolarbipolar

35. Selection Device Benchmarking u ‘Waser 2010’ (individual cell-based) v V on ~ 1 Volt  I on min ~ 1  A v J on ~10 6 A/cm 2 for L~10 nm u ‘Hwang 2010’ ( cross bar array with a 1-100 Mb block density) v V on ~ 1-5 Volt v J on ~ 10 5 – 10 6 A/cm 2 v ON/OFF > 10 7 -10 8 35 G. H. Kim, K. M. Kim, J. Y. Seok, H. J. Lee, D-Y. Cho, J. H. Han and C. S. Hwang, “A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory”, Nanotechnology 21 (2010) 385202 H. Schroeder, V. V. Zhirnov, R. K. Cavin, and R. Waser, “Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells ”, J. Appl. Phys. 107 (2010) 054517

36. I. Scaling Limits of the Schottky Diodes Energy barriers (Schottky barriers) are formed at the metal-semiconductor (insulator) interfaces space charge formation in the interface region If the barrier profile is known, the calculation of the current passing through the barrier is straightforward based on the thermionic and tunneling equations

37. Excel-based home-made diode model: A calibration C.Y. Chang, Y. K. Fang, and S. M. Sze, “Specific contact resistance of metal-semiconductor barriers”, Soli-State Electron. 14 (1971) 541-550

38. Scaling limitation: Reduction of the effective conduction area due to side depletion u If finite lateral dimensions of a 3-dimensional semiconductor structure are considered, the side interfaces can also effect the current flow. v Band bending/barrier formation usually occurs at these interfaces, and they need to be taken into account. v The band bending results in either depletion (bent up) or accumulation (bent down), and correspondingly, a layer with lower (depletion) or higher (accumulation) conductivity of width W SV is formed. u Therefore, in addition to the depletion W MS layer aligned with the direction of current (‘active’ interface, modulated by external stimulus), there is a lateral depletion layer W SV perpendicular to the current flow (‘passive’ interface, which remains more or less stable during device operation). v This ‘passive’ side interface may also effect the total current. If a depletion high- resistive layer of width W SV is formed, the effective cross-sectional area for modulated current flow is decreased. v In the case of an accumulation low-resistive layer, a parasitic surface resistor will be formed in parallel with the resistive memory element.

39. Reduction of the effective conduction area due to side depletion I min =1  A W SV L   N d  L min >2W 0

40. Scaling Limits of Diodes 40 Me Si N d ≤N C pn-diode  Esaki tunnel diode Schottky diode  Ohmic contact NdNCNdNC N C – effective density of states in the conduction band, for Si N C =2.8x10 19 cm -3

41. Schottky diode reverse current 41 V=1 Volt N=5×10 18 cm -3

42. Schottky diode reverse current 42 V=1 Volt N=10 19 cm -3

43. Schottky diode reverse current 43 V=1 Volt N=2.8×10 19 cm -3 OFF current increases with doping OFF current increases with scaling

44. Germanium Schottky diodes N C =1.04x10 19 cm -3 N d =N C and V on= 1 volt W 0 =8.7 nm L min =20 nm (I on ~ 1  A) ON/OFF ~ 10 5 Extreme scaling: ‘Relaxed’ case: N d =10 18 cm -3 L=500 nm W 0 =31 nm I on ~ 2 m A ON/OFF ~ 10 5 V off= 1 volt

45. Silicon Schottky diodes N C =2.8x10 19 cm -3 N d =N C and V on= 1 volt W 0 =6.2 nm L min =14 nm (I on ~ 1  A) ON/OFF ~ 10 7 Extreme scaling: ‘Relaxed’ case: N d =10 18 cm -3 L=300 nm W 0 =31 nm I on ~ 260  A ON/OFF ~ 10 10 V off= 1 volt

46. 46 Selector typeMaterial System V on1 I on1 V on2 I on2 ON/OFFFREF Unipolar cell pn-diodePoly-Si (E)1 20  A 2×10 4 A/cm 2 --10 5 0.3  m van Duuren 2007 Schottky diode n-ZnO (E)1 45  A 500 A/cm 2 --10 5 3  m Huby 2008 Ge NW (E)1 1  A 500 A/cm 2 --10 2 0.5  m Wong 2008 a-Si (I)1100 nA 1000 A/cm 2 --10 6 100 nmLu 2010 p-Si (E)1 10  A 1000 A/cm 2 --10 3 1  m Lee 2010 Pt/TiO 2 16 mA 10 A/cm 2 --10 9 245  m Hwang 2010 Heterojunction diode n-ZnO/p-Si325 mA 250 A/cm 2 --10 3 100  m Choi 2010 CuO/InZnO1 2.5  A 1000 A/cm 2 --10 3 0.5  m Park 2009 Bipolar cell Zener diode(E)Toda 2009 Reverse breakdown Schottky diode Cu/n-Si1 10  A -3 10  A 10 3 2  m Kozicky 2010 Complementary resistive switch Pt/GeSe/Cu/Ge Se/Pt 1 600  A 2400 A/cm 2 600  A 2400 A/cm 5  m Waser 2010 L min =20 nmON/OFF max =10 5 ON/OFF max =10 7 L min =14 nm

47. Action Items for April 2011 u To complete assessments for pn-diodes, Schottky diodes, and heterojucntion diodes v To find experimental reports on smallest diodes u To begin studies of Zener and avalanche diodes and other concepts u To begin studies of the resistive switch-type select devices v May have better scaling properties than diode-type devices

48. Selection Devices Summary u Experimental selecting devices have yet to meet the benchmark specifications v Hence, outstanding research issues persist v 2011 SD table and text will reflect both target parameters and experimental status u More detailed benchmarking and further analysis is currently underway 48

49. Timeline & Milestones u April 5 – A draft section (~ 2 paragraphs + 1 Table) for the ITRS ERD chapter u April 10 – ITRS meeting in Potsdam, Germany u July 1 - presentation draft for the ITRS meeting in SF u July 9 – ITRS meeting in SF v Wei Lu will present a technical presentation with a summary of our findings u Aug. 1 – Final materials on SD for ITRS ERD Chapter u Nov. 1 – Research paper manuscript draft complete 49

50. Solid-State Storage Class Memory

51. SCM Team: 51 Barry Schechtman (INSIC) Rod Bowman (Seagate) Geoff Burr (IBM) Bob Fontana (IBM) Michele Franceschini (IBM) Rich Freitas (IBM) Kevin Gomez (Seagate) Mark Kryder (CMU) Yale Ma (Seagate) Kroum Stoev (Western Digital) Winfried Wilcke (IBM) Thomas Vogelsang (RAMBUS) Matthew Marinella (Sandia Labs) Jim Hutchby (SRC) Victor Zhirnov (SRC)

52. Storage-class memory (SCM) u Research and development efforts are underway worldwide on several nonvolatile memory technologies that not only complement the existing memory but also reduce the distinction between memory and storage 1 v Memory: fast, evanescent, random-access, expensive v Storage: slow, permanent, sequential-access, inexpensive u Storage-class memory (SCM): Emerging solid-state technologies with (some) attributes of both memory and storage devices v May eventually replace discs and (perhaps) DRAM 1 1 “Storage-class memory: The next storage system technology”, by R. F. Freitas and W. W. Wilcke, IBM J. Res. & Dev. 52 (2008) 439

53. SCM candidates 2 and their relation to ITRS ERD chapter u FeFET u ReRAM u Solid Electrolyte u Organic … 2“Overview of candidate device technologies for storage-class memory”, by G. W. Burr et al, IBM J. Res. & Dev. 52 (2008) 449 Many of the current SCM candidates are currently present in the ITRS as memory technologies. Their potential for SCM could be included within the existing framework, e.g. as an additional table row and corresponding discussion in text. 2009 Decision: ITRS ERD will include storage-class memory (SCM) in ERD chapter

54. Draft section on SCM is Available u Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. v Such a device requires a nonvolatile memory technology that could be manufactured at a very low cost per bit. u As the scalability of flash is approaching its limit, emerging technologies for non-volatile memories need to be investigated for a potential “take over” of the scaling roadmap for flash. u In principle, such new SCM technology could engender two entirely new and distinct levels within the memory and storage hierarchy, located below off-chip DRAM and above mechanical storage, and differentiated from each other by access time. 54

55. I. S-type storage-class memory u The first new level, identified as S-type storage-class memory (S-SCM), would serve as a high-performance solid-state drive v accessed by the system I/O controller much like an HDD. v S-SCM would need to provide at least the same data retention as flash, v offering new direct overwrite and random access capabilities (which can lead to improved performance and simpler systems) v However, it would be absolutely critical that the device cost for S- SCM be no more than 1.5-2x higher than NAND flash v If the cost per bit could be driven low enough through ultrahigh memory density, ultimately such an S-SCM device could potentially replace magnetic hard-disk drives in enterprise storage server systems. 55

56. II. M-type storage-class memory u M-SCM:  should offer a read/write latency of less than 1  s. n would allow it to remain synchronous with a memory system, allowing direct connection from a memory controller and bypassing the inefficiencies of access through the I/O controller. u Would be to augment a small amount of DRAM to provide the same overall system performance as a DRAM-only system, while providing v Moderate retention, v Lower power-per-GB and lower cost-per-GB than DRAM. v Endurance is particularly critical n the time available for wear-leveling, error-correction, and other similar techniques is limited  > 10 9 cycles 56

57. Target device and system specifications for SCM 57 ParameterBenchmarkTarget HDDNAND flashMemory-typeStorage-type Read/Write latency (  s) 3000-5000~100 (block erase ~1 ms) <0.31-10 Endurance (cycles)10 5 >10 9 10 8 Retention10 years>5 days10 years Bandwidth (GB/s)0.62 GB/s>>11 ON powerTBD Lower (per GB) than Standby power<1% ON power Cost ($/GB)0.12Lower thanWithin 2-3x of NAND Flash Requisite density0.66 F 2 3F 2 (MLC)< 8F 2 < 3F 2 Mean time between failures (Mhours) TBD 22 Hard error rate, (bits/Tbyte) TBD < 10 -4 [1] [1] The endurance of the chip shouldn't be confused with the endurance of an entire SSDisk, once wear-level is employed. [2] [2] Power was not covered in any detail: TBD Action item: All numbers need to be carefully reviewed

58. SCM section in 2011 ERD u 2011: Additional rows in the Emerging Research Memory Table n Potential of current technology entries for storage-class memory n Corresponding discussion in text n Critical parameters: v Scalability v Multilevel Cell - MLC (MLC vs extreme scaling dilemma) v 3D integration (stacking) v Fabrications costs v Endurance (for M-SCM) v Power u The driving issue is to minimize the cost per bit 58

59. Potential of the current emerging research memory candidates for SCM applications 59 ParameterFerroelectric memory Nanomechanical memory Redox memory Mott Memory Macromolecular memory Molecular Memory Scalability MLC 3D integration Fabrication cost Endurance Action item 1: Corresponding discussion needs to be added to the memory text Action item 2: Decision is needed on how inclusive the SCM section should be: Should it be limited by ERD devices (table above)? OR It should include other, more matured devices, e.g. PCM, STT-MRAM, etc.?

60. Action Items for Memory (Dec. 2 & 5, 2010, ERD Meetings) u Should Storage Class Memory drive a new architecture discussion in the Architecture Section? u Advances in SCM could drive the emerging data-centric chip architectures v Nanostores u Nanostores architectures could be an important direction for the future of information processing. 60 Computer, Jan. 2011

61. Decisions for Memory Section (Dec. 2 & 5, 2010 ERD Meetings) 61 Action Items for Memory (Dec. 2 & 5, 2010, ERD Meetings) 1. Should Storage Class Memory drive a new architecture discussion in the Architecture Section? Explore a definition of SCM Zhirnov and Schechtman 5. Develop a table of Devices mapped onto materiel and their critical property required to demonstrate the key attribute of the device. Bourianoff Garner and Zhirnov 6. Rename the FeFET to include the Fe-barrier device.Zhirnov 8. Change “Nanobridge Cantilever” to just “Nanobridge”Zhirnov Put Vertical MOSFET in the Memory Section Include new section on Storage Class Memory Include new section on Select Device OK

62. ERD Memory Tasks u Update Memory Tables and Text v Implement the decisions made at the 2010 ERD FFMa s wel as at the 2010 workshops in Barza and Tsukuba n Status: work in progress n 1 st draft (tables): April 2011 n Final draft (tables + text): July 1, 2011 u Create new section on Storage Class Memory v Status: 1 st draft completed v Final draft: April 2011 u Create new section on Select Device v Status: A fundamental study is underway develop an analysis of nanoscale selector devices for memory v 1 st draft: April 2011 v Final draft: July 1, 2011 v Research paper: November 2011 62