1. Introduction to PG & LA 數位電路實驗 TA: 吳柏辰 Author: Trumen

2. Outline Programmable Data Generator Logic Analyzer Complete the RSA System 2

3. Programmable Data Generator 3

4. Introduction to PG Programmable data generator (PG in brief) is powerful of generating several kinds of digital waveforms. Combining logic analyzer (LA) and PG will make an auto testing system or auto verification system. 4

5. 5 System Properties Setup 1 2 (for GPIO) 3

6. 6 Wave Editor 1

7. Definitions Label (signal name) Labels can be defined as numeric, alphabetic, underscore _, [, or], yet their length cannot be over 31 characteristics (bytes). Channel (POD order from left to right) Pod A = CH-00 ~ CH-09 Pod B = CH-10 ~ CH-19 Extended Pod = Event_1, …, Clock_Out 7 Well, just take them as 0~9

8. Zoom in & Zoom out Note! The base point is the Address Stamp of the waveform field whenever the waveform is either zoomed in or zoomed out. 8 zoom out & zoom inAddress stamp

9. 9 Set Parameter 1

10. 10 1 2 (internal clock frequency) (keyboard event) (cursor change time gap, the cursor transformation depends on it) Cursor Drag mode When you stop the Drag cursor for a while, it will restore to Point cursor. Point mode You just move Point cursor quickly then the Point Cursor will change to be Drag cursor automatically. 3 4

11. 11 Add Label 1 2 3 4 5

12. 12 1 2 3 45 6

13. 13 1 press & drag 2 3

14. 1 2 3 14 4 5 6 7

15. 15

16. Command Setting There is one label named PG_Function in waveform field cannot be deleted. You may set PG_Function command to control the waveform output flow. 16 NameIntructionDescription NPNo OperationNo action SESet EventSet Event to be a trigger WEWait EventStop for waiting Event received ………

17. 1 2 3 4 (the ready signal) 5 1617

18. 18 1 3 2 4

19. 19

20. 20 request for a 0 Finished!!…?

21. Before Running After finished waveform check and reported no errors, you may click Run button to output these data. PC will take 0.5~1 second to transform these data into PG through USB port. The tip of running PG is to insert Set Keyboard Event and Wait Event command in the empty front area of waveform field. 21

22. 22 1 2 3 4 5

23. 23 1 3 2 4

24. 24 Finished!!!

25. 25 Save PG File 1 2 3 4

26. 26 Load PG File 1 2 3

27. 27

28. Logic Analyzer 28

29. Introduction to LA Logic Analyzer (LA in brief) is used to observe the output signals from other devices. TravelLogic series (which are used in our experiments) has 36 channels. 29

30. 30 1 2

31. 31 1

32. 32

33. 33 1 2 3 4 5,6 7

34. 34

35. 35 Trigger Position

36. 36 1 2

37. 37 The sampling rate ideally should be 5-10 times of the frequency of the target signal. 1

38. 38 1 2

39. 39

40. 40 Save LA File 1 2 3 4

41. 41 Load LA File 2 (double click) 3 1

42. Complete the RSA System 42

43. System Overview 43 PG DE2-115 LA clk _o reset _o ready _o we _o oe _o start _o reg_sel_o addr_o data_i _o data_o clk reset ready we oe start reg_sel addr data_i

44. Connect PG Components (1/3) 44

45. Connect PG Components (2/3) 45

46. Connect PG Components (3/3) 46

47. Connect LA Components (1/2) 47

48. Connect LA Components (2/2) 48

49. 49 1

50. 50 1 2 Push Space Key

51. 51

52. How to Optimize? (1/2) Modify the constraint file exp2_rsa.sdc and then compile again. Ex: Change the signal frequency of PG and check if the result is still correct. Don’t forget to change the sampling rate of LA. Record the min. clock period (max freq.). 52 create_clock -period 500 [get_ports clk] derive_clock_uncertainty set_input_delay 0 -clock clk [all_inputs] set_output_delay 0 -clock clk [all_outputs]

53. How to Optimize? (2/2) Modify the testbench clock period to min. clock period TEST_DATA to 6 Run the Verilog simulation to get the finish time. 53

54. The End. Any question?

55. Reference 1. "DE2-115 User Manual" by Terasic Technologies Inc. 2. "enPG.pdf" by Acute Technology Inc. 3. "enLA.pdf" by Acute Technology Inc. 55