1. 1 Amit Berman Reliable Architecture for Flash Memory Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar Department of Electrical Engineering, Technion – Israel Institute of Technology

2. 2 Agenda  Reliability in Flash Memory  “Reliable Architecture”  The advantages of “Reliable Architecture” Density Performance  Conclusions

3. 3 Introduction  Reliability: a crucial factor in flash memory design  Quantification: Guaranteed # of times that a memory cell can be written and erased before an error occurs Our goal is to reduce the number of physical write/erase operations of the flash memory cells Basic physical characteristic of flash memory cell: every write/erase operation, the memory cell is degraded Eventually, there would be a data error in the memory cell, proportional to the number of write/erase operations Analogy : Flash memory cell as a glass of water Level-1 -1 -1 The amount of water in the glass represents the information Each time we will fill and empty the glass – it will be cracked

4. 4 1 bit per cell (1BPC) Ref # of cells Vt Erased Programmed :Level 1 0 :Bit Empty Full Ref 2 # of cells Vt 0 1 2 3 :Level Ref 3 Ref 1 11 10 01 00 :Bit Level-0 -1 -2 -3 -0 -0 -0 -1 -1 -1 -2 -2 -2 -3 -3 -3 -3 Reliability is important for density  Bad reliability low density  Good reliability high density 2 bits per cell (2BPC) “fewer glass cracks, low water leakage”  we can distinguish between more levels Reliable Architecture technique increase the reliability We can use it to increase the density and keep constant reliability Increase density  decrease reliability

5. 5 Reliability is important for performance Ref 2 # of cells Vt 0 1 2 3 :Level Ref 3 Ref 1 11 10 01 00 :Bit  Bad reliability low writing speed  Good reliability high writing speed Ref 2 # of cells Vt 0 1 2 3 :Level Ref 3 Ref 1 11 10 01 00 :Bit Level-0 -2 -0 -0 -0 -2 -2 -2 -0 -2 -0 -0 -0 -2 -2 -2 -0 -0 -0 -0 “glass cracks makes it hard to fill it”

6. 6 Related Work  Coding  MFG Process * M. Schwartz, S. Bruck “Rank Modulation for Flash Memories” * M. Yanai, I. Bloom “NROM memory cell design”

7. 7 Observation  Flash data is erased in blocks (e.g. 64KB)  There are redundant write and erase operations The memory needs to be erased in order to write new information Erase operation lasts long (e.g. 1.5mS)  cells are erased in groups erase write The cell returned to its original level

8. 8 Observation: Example Vt Time T3 T2 T1  There are redundant write and erase operations At time T1, information is written Block is erased to enable new write New write is same as the initial value In this process there are total 2 writes and 1 erase operations, can we reduce it to 1 write operation?

9. 9  New concept of operating flash memory Common Architecture vs. Reliable Architecture Reliable Architecture Write Re-write Erase Virtual Erase Read (no change)

10. 10 Flash Re-write Concept read the stored data, compare it to the input data and adjust for the difference if exists Re-write concept read and adjust If equal: do nothing If difference: adjust

11. 11  Virtual erase process: when erase is applied to a certain block/page  Mark a flag in the spare memory array for erase indication Virtual erase concept  Data is not physically erased Non-Volatile Memory Array Spare NVM Valid Indication Control Logic Analog HV I/O erase virtual erase flag  Construct a “spare memory array” that contain information about erase status

12. 12 Reliable Architecture: changes to the current architecture  Target: Avoid redundant write and erase operations  Changes: Arrange the memory array so that erase in a single cell is enabled Change the control logic for the new operations Add spare memory cells for virtual erase operation

13. 13 Analysis : symmetric binary source NT=# of bits with no transition l= # of flash memory levels n= # of bits in a page While applying memory write, average # of cells with no transition: Average # of cells with write transition: Average # of cells with erase transition:

14. 14 Example 25% of the memory cells have write transition 25% of the memory cells have erase transition For 2-levels flash with random input data source:  Saves 50% of write/erase operations, x2 improvement  Each writing operation 50% of the memory cells hold the same value * Taking into account Gaussian distribution

15. 15 Reliability Improvement Factor (RIF) while using Reliable Architecture RIF is lower bound since we also save some transitions between levels

16. 16 Performance analysis Erase Operation ~1.5ms Write Operation ~0.8ms (2KB page)  In a large page size, the write performance is better then the one in common architecture  On small page size, the erase transition reduce performance Writing is done sequentially due to current consumption limitations Erase can be done in parallel, for any # of memory cells  The Reliable Architecture re-write concept uses the erase operation on some of the cells  Reliable architecture has advantage in large page size:

17. 17 Performance analysis  Modeling results of flash memory cells, write and erase operations with varying page size, utilizing a symmetric data source *MATLAB Reliable Architecture is effective in large page size (>8KB)

18. 18 Summary  Reliable Architecture improves reliability by the elimination of the redundant write/erase operations to the flash memory  Reliable Architecture statistically improves flash memory reliability  Reliable Architecture is improving the write performance in page size >8KB in a smaller page size, write performance is reduced Can be used to increase reliability Can be use to increase density and keep reliability constant

19. 19 Questions? High Density Low $/MB Nonvolatile Updateable ROM EPROM DRAM EEPROM SRAM