1. Chapter 13 Future Directions 學生：郭智昇 學號： R91943036

2. Technology Trends

3. SiGe HBT can be viewed as an “ adder ” to a high-speed CMOS core technology without perturbing the characteristics of the underlying core CMOS

5. SiGe 有優於 GaAs 的高集積度、高電子傳導率與 高製造良率的競爭優勢 與矽比較， SiGe 在高頻環境下擁有低雜訊、低 功率損耗的優點 可同時整合 FET 與 Bipolar 也是 SiGe 的發展優勢 SiGe 的用途涵蓋功率放大器、無線通訊的行動 電話、 Bluetooth 、 DECT 等之 RF IC 、 SoC 或光 纖骨幹網路 SONET 介面 IC

6. SiGe 製程技術 HBT HFET Optoelectronic

7. SiGe HBT 與 Si-Bipolar 相容，可透過三種 不同的磊晶成長技術 -Selective 、 Differential 、 Blanket 發展 SiGe HBT 元件結構分成 Doublepoly Selfaligned 、 Singlepoly Quasi- selfaligned 、 Mesatype

8. SiGe HFET 元件結構分成 MOSFET 與 QW MOSFET 二種，其中 QW MOSFET 適用於 低電壓及高傳輸率的系統環境 Optoelectronic 發展目的完全以光電 IC 為 主，包含光電檢測器、光纖節點、光纖 高速 IC 、光導波管、光波通訊微機電開 關等

9. Technology Trends Multiple breakdown voltage versions of the core SiGe HBT will be available on the same die for greater circuit design flexibility Carbon doping of SiGe HBT will become the mainstream makes thermal budget and profile control that much easier

10. Technology Trends Higher C content(2-3%) to produce SiGeC alloys that are lattice-matched directly to Si While SiGeC alloys with up to 3% C,it seems unlikely that lattice-matching within the SiGe/Si system

11. Technology Trends First generation SiGe HBT f T,Peak =50 GHz Second generation performance level 100—120 GHz peak f T Third generation performance level >200 GHz peak f T

12. Technology Trends SiGe technology will increaseingly move to full copper metalization to support the requisite high device current densities as well as improve the Qs of the passives

13. Four approaches that might be used to improve the high-freq losses in SiGe (1)Move to high-resistivity substrates (2)Use thicker top-side dielectrics,combined with lower resistivity metal(Cu) (3)use postfabrication spun-on polymers followed by Cu or Au for passives and transmission lines (4)move to SiGe on SOI

14. Noise coupling Using conservative layout approaches and intelligent placement of critical noise sensitive functions e.g. do not put your LNA next to a large CMOS digital switching block Deep-trench feature provides excellent noise isolation

16. Performance Limits

17. The peak f T in each SiGe technology generation occurs at roughly the same bias current meaning that the collector current density is rising rapidly the level of demonstrated performance Power saving potential for SiGe clearly holds great leverage for portable(battery-limited) system

19. What is the practical performance limit of a commercially visible SiGe HBT technology? Attainable f max is difficult Breakdown voltage must decrease as the transistor performance improve