1. Summary Actel ProAsic/3E Irradiation Tests Antonio Pellegrino (work by Syracuse group) Nikhef, OT FE Architecture Mini-Review 06-03-2013 o introduction doses o irradiation tests work done by SPECS group work done by Syracuse group o summary & outlook

2. 1 Radiation Dose estimates (see M. Karacson talk at 14 Feb Electronics meeting) OT FE Boxes (T1) Dose per collision (Gy)

3. 2 Radiation Dose estimates (cont’d) (see M. Karacson talk at 14 Feb Electronics meeting) At FE location of T3 : ~2  10 -14 Gray per collision Assume (  el+inel = 72 mb) 0.72  10 14 collisions per fb -1 N(L,  el+inel ) = L·  el+inel  N(1fb -1,72mb) = 10 15 b -1 ·72  10 -3 b = 0.72  10 14 At FE location of T3 : ~1.44 Gray (0.144 krad) per fb -1 e.g. ~7.2 krad for 50 fb -1 Adopting a factor 2 safety for the simulation uncertainty and another factor 2 safety for the FE irradiation tests a good figure to remember as radiation-hardness specification is ~30 krad http://lhc-statistics.web.cern.ch/LHC-Statistics/http://lhc-statistics.web.cern.ch/LHC-Statistics/ : 73d,17h,45m stable-beam  2012 LHC ~0.637  10 7 s L(1y LHC,10  10 32 cm -2 s -1 ) = 0.637  10 7 s · 10 33  10 -24 b -1 s -1 = 6.37 fb -1 to get the feeling…

4. 3 A word about FPGA’s ALTERA ARRIA GX FPGA 35K 780FBGA (EP1AGX35DF780I6)EP1AGX35DF780I6 90-nm process technology (Arria II family 40-nm) based on technology of Altera's Stratix ® II GX FPGA Actel ProAsic3/E A3PE1500 (A3PE1500-2FGG484)A3PE1500-2FGG484 130-nm process technology based on nonvolatile flash technology Heidelberg design based on: Nikhef design based on: Background consideration: nonvolatile flash technology should be more radiation-tolerant (also already experience with SPECS and TFC-FAN FPGAs in CtrlBox). However, processes that combine Flash and CMOS are typically 2-3 generations behind leading-edge CMOS processes used by SRAM-based FPGAs. Irradiation Tests mandatory!

5. 4 Irradiation Tests Actel ProAsic3E o see talk by R. Mountain in LHCb Electronis Upgrade Meeting 14/Oct/2010R. Mountain in LHCb Electronis Upgrade Meeting 14/Oct/2010 o see talk by R. Mountain in LHCb Electronis Upgrade Meeting 21/Jul/2011R. Mountain in LHCb Electronis Upgrade Meeting 21/Jul/2011 roughly reproduce results from SPECS test RAM: few SEU every 3min run (few krad per run) similarly for Flash ROM o see talk by JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012 dedicated test of PLL and Nikhef TDC firmware (see next slides) SPECS project tested Proasic already in 2004 (SPECS + TFC-fan in CtrlBox) (D. Breton, J. Lefrançois et al., unpublished) programmable up to ~17 krad still functioning until ~30 krad, then high current and malfunction Tests of 3APE1500(-2) in 2010-2012 with 200Mev protons at Boston hospital ( Syracuse University, M. Artuso, E. Cowan, Bin Gui, D. Hsu, R. Mountain, JC Wang)

6. 5 Actel Tests – People & Setup Front Back Alignment Laser spot Alignment Laser spot Proton Radio-Chromatograph ~28 mm (package) Position (cm) Relative Flux 226 MeV proton beam test 2 Actel’s at a time “back” 68% radiation of “front”

7. 6 Actel PLL & TDC Test Setup Set a 5-bit number for comparator to check against measured TDC (Nikhef + Syracuse) Twisted pair cable provides delay for TDC to measure Generate two 320 MHz and one 80 MHz clocks of fixed phases Measure 40 MHz time signal, with 1280 MHz equivalent precision. Check if frequencies of produced clocks are correct Check if measured TDC value agrees with U13/14 Record during 3min (2 33 BX’s) runs (~2 krad)

8. 7 Irradiation Dose Actel PLL & TDC Chips are tested in pairs FPGA 4 (front) & FPGA 3 (back) FPGA 2 (front) & FPGA 1 (back) FPGA J (front) & FPGA L (back) Dose(back) ~ 68% Dose(front) All FPGAs receives 30 kRad or more, except for FPGA 1 that was intentionally removed for other tests talk by JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012

9. 8 Irradiation Results Actel PLL & TDC Near station Computer crashed Verification OK Reconfiguration OK Verification OK 38 1.2x10 9 1 Verification failed Reconfiguration failed x3 Power-cycle reconfiguration failed Change comparator value to 11: large error count is seen. Change back to 10. 37 Results for FPGA 2 (received 45.6 krad) PLL lock error. (run was with high intensity) LED indicates TDC = 12 talk by JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012

10. 9 Summary irradiation tests Actel talk by JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012JC Wang in LHCb Electronics Upgrade Meeting 14/Feb/2012 talk by R. Mountain in LHCb Electronis Upgrade Meeting 14/Oct/2010R. Mountain in LHCb Electronis Upgrade Meeting 14/Oct/2010 talk by R. Mountain in LHCb Electronis Upgrade Meeting 21/Jul/2011R. Mountain in LHCb Electronis Upgrade Meeting 21/Jul/2011 o programmable up to ~17 krad o still functioning until ~30 krad, then high current and malfunction o RAM: few SEU every 3min run (few krad per run) o after irradiation, all chips fail firmware verification and reconfiguration o but they still seem to function as TDC’s o hardly any PLL lock lost o few TDC errors up to ~30 krad, then TDC values seem to “shift” Preliminary Write-up with final analysis forthcoming Major thanks to Erika, Marina, Bin, Dylan, JC, Ray etc. Actel kind of “passes” the tests, but margin quite narrow... (future generation from Microsemi 100 krad TID in 65-nm tech?) (if enough manpower at Nikhef, also looking at SMARTFUSION2, IGLOO2)