1. Synopsys Low Power Solutions for ASIC Design Flow

2. 2 © 1998 Synopsys, Inc. Confidential & Proprietary Outline qMarket Drivers qSynopsys Low Power Solution qDesignPower qPower Compiler qMarket Drivers qSynopsys Low Power Solution qDesignPower qPower Compiler

3. 3 © 1998 Synopsys, Inc. Confidential & Proprietary Technology Trend 13% 39% 10% 8% 24% 6% Synopsys Revenue Networking 26% CAGR Wireless 24% CAGR Computers / Peripherals 15% CAGR Microprocessor 20% CAGR Increasing Complexity & Integration Higher Performance, Lower Power, Lower Cost Source: Dataquest (Projected CAGRs, 1996-2000)

4. 4 © 1998 Synopsys, Inc. Confidential & Proprietary Power Issues are Business Issues qRisk l A field failure could cost millions of dollars qProfitability l The package cost exceeds the target device price qCompetitiveness l The competing product has longer battery life with more functionality

5. 5 © 1998 Synopsys, Inc. Confidential & Proprietary The Traditional Medicine No Longer Works qSpreadsheet based power estimation l Not accurate enough (short-circuit power ~30%) l Various modules require different formulas (datapath, memory) qReduced supply voltage l Should be carefully traded-off with performance qSmaller geometry l Is usually coupled with increased # of transistors on a chip qManual implementation of power reduction techniques l Reduces designers productivity and impacts Time-To- Market

6. 6 © 1998 Synopsys, Inc. Confidential & Proprietary Complete Spectrum of Low Power Solutions RTL Gate Transistor Polygon Optimization Analysis Extraction and Characterization Power Compiler AMPS Arcadia PowerArc DesignPower PowerGate RailMill PowerMill if (a<b) then z <= ‘1’ else z <= ‘0’

7. 7 © 1998 Synopsys, Inc. Confidential & Proprietary Synopsys’ Complete Low Power Methodology Custom FlowASIC Flow Transistor level Power Analysis & Diagnosis Extraction Schematic Transistor level Power Optimization Layout Compile (DC) Gate level Power Optimization RTL Power Optimization Place & Route Power Analysis RTL Source Full Chip Net List Full Chip Power Analysis Gate level Power Analysis

8. 8 © 1998 Synopsys, Inc. Confidential & Proprietary Power Library Infrastructure &Power Library is the Infrastructure for accurate Power Analysis and Optimization 4 Robust Power Modeling 4 Automatic Characterization 4 Unified power library 4 Broad library support

9. 9 © 1998 Synopsys, Inc. Confidential & Proprietary Dynamic Switching Power (I sw ) [70-90%]  Also referred to as capacitive power P switching = 1/2 * V 2 x  [ C i x TR i ] Internal (Short-Circuit) Power (I int ) [10-30%]  Also referred to as short circuit power P internal =  E int i (Output load, input transition) x TR i Static Leakage Power (I leak ) [<< 1%]  Sub-threshold leakage dominates, some due to leakage substrate P leak =  P leak i Robust Power Modeling V t Input transition P N Vdd Gnd InOut I sw I leak I int C load Complete power model provides infrastructure for analysis and optimization for all nets i for all cells i for all cells i

10. 10 © 1998 Synopsys, Inc. Confidential & Proprietary Robust Power Modeling (cont.) qState-dependent power model DATAIN ADDRESS CLK RD_WR CS DATAOUT RAM Power consumption varies with various operation modes A B C D E Z Cell XYZ qPath-dependent power model Power consumption varies with various input to output paths Accurate analysis for state- and path-dependent functions such as RAMs, I/Os and multilevel cells Accurate analysis for state- and path-dependent functions such as RAMs, I/Os and multilevel cells

11. 11 © 1998 Synopsys, Inc. Confidential & Proprietary PowerArc for Library Characterization PowerGate DesignPower Power Compiler Library Compiler PowerArc SPICE Netlists Process Specs. Current Synopsys Lib. 4Automatic, accurate characterization for cells and megacells 4The same library shared by all gate- level tools 4Availability September 98 Synopsys.lib + Power Synopsys.db Synopsys.lib

12. 12 © 1998 Synopsys, Inc. Confidential & Proprietary The Most Comprehensive Library Support in the Industry ASIC/Library VendorStatus Alcatel MietecAvailable Now FujitsuAvailable Now GEC PlesseyAvailable Now IBMAvailable Now Lucent TechnologiesAvailable Now LSI LogicAvailable Now MotorolaAvailable Now NECAvailable Now SGS ThomsonAvailable Now Symbios LogicAvailable Now Temic-Matra MHSAvailable Now Texas InstrumentAvailable Now TSMC CBAAvailable Now ArtisanAvailable Now SamsungAvailable Now ASIC/Library VendorAvailability Seiko/EpsonAvailable Now SonyAvailable Now Lucky GoldstarUnder development RohmUnder development RicohAvailable Now Toshiba Available Now OKI SemiconductorAvailable Now MatsushitaAvailable Now MitsubishiAvailable Now HitachiAvailable Now AspecAvailable Now VLSI Technology Available Now

13. 13 © 1998 Synopsys, Inc. Confidential & Proprietary Power Analysis is a Key Enabling Technology qPower Analysis is essential for Low Power Management l Fast and accurate analysis early in the design process  Enables creation of low power designs  Drives knowledge-based architectural and implementation decisions l Detailed and comprehensive analysis at the later stages  Ensure that power budget and constraints are satisfied  Power Signoff

14. 14 © 1998 Synopsys, Inc. Confidential & Proprietary DesignPower for Early Power Analysis qEarly visibility into the power consumption l Focus your efforts where the opportunities are l Power budgeting l Fast tradeoff analysis for power Analysis is the enabling technology to design for low power RTL Design Design Compiler Power Compiler (RTL Clock Gating) PowerGate Place & Route Power optimized design DesignPower

15. 15 © 1998 Synopsys, Inc. Confidential & Proprietary The Problem: Power budget was exceeded on AM2910 design Proposed Solution: Identify power hungry modules and look for opportunities to reduce power Identification of Power Problems Stack Module Cell Driven Net Tot Dynamic Cell Internal Switching Power Leakage Cell Power Power (% Cell/Tot) Power Attrs -------------------------------------------------------------------------------------------------------- STACK_BLK 247.1813 1486.9333 1734.115 (14%) 295.8000 h REG_BLK 24.8037 700.8896 725.693 (3%) 29.7000 h UPC_BLK 12.6486 679.9627 692.611 (2%) 13.2000 h MUX_OUT_BLK 35.3713 201.3174 236.689 (15%) 27.0000 h CNTL_BLK 22.1711 111.6987 133.870 (17%) 16.2000 h -------------------------------------------------------------------------------------------------------- Totals (5 cells) 34.218uW 318.080uW 352.298uW (10%) 381.900nW DesignPower quickly isolates power problems

16. 16 © 1998 Synopsys, Inc. Confidential & Proprietary DesignPower Enables Intelligent Decisions No performance impact! Ungated DesignPercentage of time in write cycle Original Area1730 Equivalent Gates Gated Area1528 Equivalent Gates Original5%.....50%....95% 45 50 55 60 65 70 75 80 Power Tradeoffs for AM2910 Stack DesignPower quantifies power savings The Problem: The stack module of the AM2910 was consuming too much power Proposed Solution: Gate the clock so that the registers are only clocked during the write cycles

17. 17 © 1998 Synopsys, Inc. Confidential & Proprietary Early Analysis Leads to Power Savings National Semiconductor Success A LAN switch ASIC of 200K gates and 41 memories characterized for state-dependent power. DesignPower revealed excessive power consumption by the memories due to redundant read cycles. The RTL was fixed and the power consumption reduced

18. 18 © 1998 Synopsys, Inc. Confidential & Proprietary DesignPower: inputs & outputs DesignPower Gate-Level Netlist Power Report  Total Design  Modules  Individual Nets  Individual Cells VHDL or Verilog RTL Simulation VHDL or Verilog RTL Simulation Library Switching Activity Information VHDL or Verilog Gate-Level Simulation VHDL or Verilog Gate-Level Simulation

19. 19 © 1998 Synopsys, Inc. Confidential & Proprietary Switching Activity Information (DESIGN "ex") (TIMESCALE 1ns ) (DURATION 1000 ) (INSTANCE E/E2 (INSTANCE TOP (PORT (DINA (TC 500) (T1 400) (T0 504) (TX 96) ) (COUNT (TC 4328) (T1 783) (T0 217) ) ) ( INSTANCE U_VA_30 (NET (CI (TC 800) (T1 300) (T0 600) (TX 100) ) (SO (TC 815) (T1 300) (T0 249) (TX 451) ) ) (DESIGN "ex") (TIMESCALE 1ns ) (DURATION 1000 ) (INSTANCE E/E2 (INSTANCE TOP (PORT (DINA (TC 500) (T1 400) (T0 504) (TX 96) ) (COUNT (TC 4328) (T1 783) (T0 217) ) ) ( INSTANCE U_VA_30 (NET (CI (TC 800) (T1 300) (T0 600) (TX 100) ) (SO (TC 815) (T1 300) (T0 249) (TX 451) ) ) # of togglesTime in ‘1’Time in ‘0’Time in ‘x’ qToggle-Rate (Tr) is the number of toggles per time-unit, and is used for the power calculation. Tr = TC / DURATION qStatic-Probability (Sp) is the portion of time a node is at a logic value of “1”, and is used for switching activity propagation and power calculation. Sp = T1 / (T1 + T0 + TX) Example: Switching Activity Interchange Format (SAIF)

20. 20 © 1998 Synopsys, Inc. Confidential & Proprietary Switching Activity Generation - RTL qActivity of the synthesis invariant nodes is captured during RTL simulation l sequential outputs, hierarchical boundaries, black-box pins qUtilizes a zero-delay cycle-based propagation engine qSame activity is used for both analysis and optimization qNew switching activity is required when the synthesis invariant behavior is changed

21. 21 © 1998 Synopsys, Inc. Confidential & Proprietary RTL Switching Activity Flow qSAIF (fwd) includes the RTL constructs to be monitored qSAIF (back) includes the switching activity of these constructs RTL Design HDL Compiler SAIF (fwd) RTL Simulation VCD SAIF (back) VCD

22. 22 © 1998 Synopsys, Inc. Confidential & Proprietary Gate-Level Switching Activity Flow Gate-Level Design Library Compiler SAIF (lib) Gate-Level Simulation SAIF (back) sim2dp qSwitching activity for most of the nodes is captured during gate-level simulation

23. 23 © 1998 Synopsys, Inc. Confidential & Proprietary Switching Activity: RTL vs. Gate-Level qRTL Switching Activity: Available early in the design process Fast Accurate  Does not account for glitches  Does not fully support state- and path-dependency qGate-Level Switching Activity: Very accurate Accounts for glitches State- and path-dependency support  Requires lengthy gate-level simulation  Usually done at the later stages of the design process Mega MegaCells Memory µp µc A/D DMA D/A S/P P/S ControlLogic

24. 24 © 1998 Synopsys, Inc. Confidential & Proprietary Simulation Interface AbstractionVerilog-XLVCSVSSMTIIKOS RTLSAIF (PLI)SAIF (PLI)VCDVCDVCDVCD Gate-LevelSAIF (PLI)SAIF (PLI)SAIFsim2dpSAIF DesignPower and Power Compiler PowerGate Abstraction Verilog-XLVCS Gate-LevelPIF (PLI)PIF (PLI) (Oct 1998)

25. 25 © 1998 Synopsys, Inc. Confidential & Proprietary PowerGate for Detailed Power qPower verification at the later stages of the design cycle l Ensure that power budget and constraints are satisfied l Time based, peak power and time-average power at user-defined intervals l Identify power hungry vectors / instructions l Isolate power problems in-time RTL Design Design Compiler Power Compiler (RTL Clock Gating) PowerGate Place & Route Power optimized design DesignPower

26. 26 © 1998 Synopsys, Inc. Confidential & Proprietary The average power consumption looks O.K yet is there a problem with the memory? Is the memory cycle valid? (address collision) Is there data contention? (are both ports in the read mode?) Address 1Address 2 Control Logic 1 Dual-port RAM Common Data Bus Control Logic 2 Identify Excessive Power In Time Power Time Average

27. 27 © 1998 Synopsys, Inc. Confidential & Proprietary Power Compiler 8/1997 RTL 10/1996 Gate Level HIndustry's first and only RTL & Gate-Level power optimizer HPush-Button power reduction at RT and Gate Levels

28. 28 © 1998 Synopsys, Inc. Confidential & Proprietary Power Compiler @ RTL Push-button reduction in power at the RT-Level RTL Source Power Compiler Clock-Gating (elaborate -gate_clock) Design Compiler Un-mapped Net-List + Constraints RTL Clock-Gating :No changes required to the RTL code :Can deliver significant reduction in power :Power reduction is design dependent 9 We have seen 30% - 60% power reduction in some designs Downstream Dependencies 4Logic Synthesis 4Testability 4Clock Tree Synthesis

29. 29 © 1998 Synopsys, Inc. Confidential & Proprietary Automatic Clock-Gating @ RTL Synchronous-load-enable implementation Gated clock implementation EN CLK FSM D_in D_out Register Bank D_out CLK FSM Latch D_in EN G_CLK Register Bank Always @ (posedge CLK) if (EN) D_out = D_in Always @ (posedge CLK) if (EN) D_out = D_in elaborate -gate_clock elaborate

30. 30 © 1998 Synopsys, Inc. Confidential & Proprietary Clock-Gating @ RTL - Power Savings Power Savings by clock-gating ¶Reduced internal power consumption at the clock-gated flip-flops ·No need for Muxes to re-circulate the data for these flip-flops (saves Power & Area) ¸Reduced power consumption by the clock network Power Saving dependency :# of load-enable registers :% of disabled cycles D_out CLK FSM Latch D_in EN G_CLK Register Bank 1 2 3

31. 31 © 1998 Synopsys, Inc. Confidential & Proprietary Clock-Gating Styles Extensive user control :Latch-based or latch-free gating style :Which register banks to gate or exclude from gating :Positive (AND) or negative (OR) gating logic :Minimal bit-width of gated registers EN CLK GCLK Latch-free {OR} EN CLK GCLK Latch-free {INV NAND BUF} EN CLK GCLK Latch-based {NAND INV}

32. 32 © 1998 Synopsys, Inc. Confidential & Proprietary RTL Clock-Gating - Report =============================================================================== | | Included | Width | Enable | Setup | Clock | | Flip-Flop Name (Bit-Width) | Excluded | Cond. | Cond. | Cond. | Gated | =============================================================================== | out1_reg (8) | - | yes | yes | yes | yes | | out2_reg (2) | - | no | yes | yes | no | =============================================================================== Summary: Flip-Flops Banks Bit-Width number percentage number percentage Clock gated (total): 1 50 8 80 Clock not gated because Bank was excluded: 0 0 0 0 Bank width too small: 1 50 2 20 Bank always enabled: 0 0 0 0 Setup condition violated: 0 0 0 0 Total: 2 100 10 100 Information: The following instances of design SNPS_CLOCK_GATE_HIGH_ have been created and must be uniquified for a hierarchical compile: clk_gate_out1_reg clk_gate_out2_reg

33. 33 © 1998 Synopsys, Inc. Confidential & Proprietary Clock-Gating @ RTL - Dependencies qLogic Synthesis 4 Power Compiler automatically generates set-up and hold constraints on the gating element 4 Combinatorial set-up and hold checks are performed by DC qTestability 4 Medium and high testability options for controllability & observability of the enable signal 4 Test Compiler and DC XP can handle the gating circuitry during rule- checking and ATPG qClock-Tree-Synthesis 4 Supported by many ASIC vendors and tools providers l Contact your vendor for details

34. 34 © 1998 Synopsys, Inc. Confidential & Proprietary Clock-Gating - Medium Testability 9TEST_MODE enables override of clock-gating during scan-in and scan-out 6Asserting TEST_MODE during the parallel mode will make FSM faults un-testable CLK FSM Latch D_in EN G_CLK Register Bank TEST_MODE D_out

35. 35 © 1998 Synopsys, Inc. Confidential & Proprietary Clock-Gating - High Testability CLK FSM Latch D_in EN G_CLK Register Bank D_out CLK TEST_MODE Observability Register Other Observability Nodes 9All FSM faults are testable 9Testability logic does not consume power 6Higher area cost

36. 36 © 1998 Synopsys, Inc. Confidential & Proprietary Tech Library Power Compiler @ Gate-Level Power Compiler dc_shell> compile -incremental Gate-Level Netlist Gate-Level Netlist Switching Activity Constraints (timing, power, area) Constraints (timing, power, area) Parasitic (Capacitance) Parasitic (Capacitance) Power Optimized Gate-Level Netlist Power Optimized Gate-Level Netlist Design Compiler

37. 37 © 1998 Synopsys, Inc. Confidential & Proprietary Power Compiler @ Gate-Level qOptimizes power simultaneously with area and timing qNew optimization technologies added for power l Activity-based optimizations minimize power subject to power constraints l Power added to the synthesis optimization cost function l 10% - 20% push-button reduction in power qWorks within timing constraints l no increase in negative slack qRequires synthesis libraries updated for power qCompletely integrated with Links-to-Layout methodology

38. 38 © 1998 Synopsys, Inc. Confidential & Proprietary Optimization Priorities Power Compiler works within the specified timing constraints Cost Type Design Rule Delay Dynamic Power Leakage Power Area Constraints Max Trans, Max Fanout Clock Period, Max_delay, Min_delay Max Dynamic Power Max Leakage Power Max Area Priority qThe optimization priorities are hard coded qTry tightening/loosening the constraints to get the required speed/power/area trade-offs

39. 39 © 1998 Synopsys, Inc. Confidential & Proprietary Cell Sizing Example Delay (a,f) : reqd = 4, actual = 3.5 Cload: f = 3; n1 = 2.5, n2 = 1.5 TR: a, b =.25, c, d =.5 => n1 =.125, n2 =.25, f =.56 Power = 3.69 Delay (a,f) : reqd = 4, actual = 3.3 Cload: f = 4; n1, n2 = 2 TR: a, b =.25, c, d =.5 => n1 =.125, n2 =.25, f =.56 Power = 4.125 Note: Internal power effects (i.e. edge rate) also considered a n2 b n1 c d f an2c an2a a n2 b n1 c d f an2a an2c Critical path Low activity net Sized up Sized down

40. 40 © 1998 Synopsys, Inc. Confidential & Proprietary Factoring Example Function: f = ab + bc + cd The function f is not on the critical path The signals a, b, c and d are all the same bit width Signal b is a high activity net The two implementations below are equivalent from both timing and area criteria Net Result: network toggling and power is reduced f = b(a + c) + cdf = ab + c (b + d) f a c c d b f d b b a c

41. 41 © 1998 Synopsys, Inc. Confidential & Proprietary Pin Swapping Example f C pin = 1.5C 1 C pin = C 1 toggle rate =.4 toggle rate =.8 b a c d f C pin = 1.5C 1 C pin = C 1 toggle rate =.8 toggle rate =.4 d b c a Move high toggle nets to lower capacitance pins

42. 42 © 1998 Synopsys, Inc. Confidential & Proprietary Phase Assignment Example Implementation tradeoff criteria:  toggle rates of inputs and outputs  pin capacitance of library cell Solution requires:  dynamic power cost function  actual toggle rates  accurate cell libraries ? 1 2 : 1 Mux 6 area = 7 A B TR =.7 TR =.3 area = 6 1 2 : 1 Mux 5 B A TR =.7 TR =.3

43. 43 © 1998 Synopsys, Inc. Confidential & Proprietary Push-Button Power Reduction by Power Compiler Intel Success (Presented by Intel at SNUG 1998) A graphics chip for which both power and area are critical, synthesized to 0.35  library at 3.3 Volts. Achieved 12%, 21% and 24% reduction in power on 3 blocks with 2% or less area increase. Lucent Success An ISDN Transceiver ASIC, 40K gates block, synthesized to 0.35  library Achieved 12% push-button power reduction with 3.3% area increase

44. 44 © 1998 Synopsys, Inc. Confidential & Proprietary ASIC Low-Power Methodology RTL Design Design Compiler Power Compiler RTL Simulation Power Compiler (RTL Clock Gating) DesignPower PowerGate Place & Route Gate Simulation RTL SA SA Cap. SNPS.db Power optimized design DesignPower RTL SA Design Exploration Design Implementation Physical Design Speed Accuracy Diagnosis

45. 45 © 1998 Synopsys, Inc. Confidential & Proprietary Links-to-Layout for Power Before: timing constraints not met Power Compiler Power Compiler Physical Design Met Constraints? PDEF set_load Yes No Floorplan Manager Floorplan Manager After: timing constraints met Lowest power implementation The lowest power silicon within your timing constraints SDF

46. 46 © 1998 Synopsys, Inc. Confidential & Proprietary Summary qPower Analysis l Early visibility into the power dissipation l Evaluate architectural and implementation tradeoffs l Detailed and comprehensive analysis at the later stages of the design cycle qPower Optimization l Push-button power reduction at RT and Gate levels l Simultaneous optimization for timing, power and area l RTL simulation support for gate-level optimization qSynopsys provides a Complete Solution l A complete set of power analysis, optimization and diagnosis tools l RT, Gate and transistor level support