1. Basic Organization

2. Our Progress Covered level 0 Ch 4: – Preview level 2 – Level 1

3. CPU Basics Primary CPU structures : datapath and the control unit – Datapath : arithmetic-logic unit and storage (registers/memory) interconnected by a data bus

4. CPU Basics Primary CPU structures : datapath and the control unit – Control Unit : Selects and sequences active circuits. Hardware or software based.

5. Registers Registers hold data for rapid access –Register : immediate –Main memory : ~60ns / ~200 clock cycles Implemented using D flip-flops The control unit determines which registers active

6. ALU Arithmetic-logic unit (ALU) –Two input busses, one output bus –Control unit sends function select

7. Busses Bus : set of wire that simultaneously convey a set of related bits –Classify by Type : point-to-point vs multipoint Width : parallel vs serial Timing : synchronous vs asynchronous

8. Busses Bus connections Point to Point:Multipoint:

9. Bus Arbitration Strategies for controlling who talks: Distributed using self- detection: Devices decide which gets the bus among themselves Distributed using collision- detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again Daisy chain: Pass authorization from hi priority to low Centralized parallel: Each device is directly connected to an arbitration circuit

10. Busses Bus connections Parallel: Serial:

11. Bus Organization Efficiency through special purpose sub-busses – Data – Address – Control

12. Busses Bus timing –Synchronous : Clock based Must avoid skew Strict timing window –Asynchronous : Handshake based Protocol based communication –I'm ready to talk –OK, I'm ready, send –Send data –Acknowledge data Part B Clock Part A

13. Bus Length Electrical signals limited to about 1/2 speed of light: ~15 cm/nanosecond Given 3 Gigahertz clock –3 billion ticks per second –0.33 ns/clock tick –Signal only travels 5cm per clock tick

14. Clocks Different subsystems, different clocks Pentium IIi7

15. Clock Clock speed != performance – Just one factor Clock Length (Inverse of speed)

16. PentiumIvy Bridge Clock Speed of instructions

17. Clock Expressive power of instructions Can I multiply in one instruction? Can I add two whole arrays in one instruction?

18. Memory Organization Idealized memory vs reality x

19. Memory Organization Memory size – Addresses x size of addressable unit – 512K x 8bits – 4 mega bits total data 512K= 512 * 1024 = 2 9 * 2 10 = 2 19 = 19 bit addresses x

20. Other Memory Other ways to make 4 mega bits – 4M x 1bit 4M addresses = 22 bit address, word size 1 bit – 256K x 16bits 256K addresses = 18 bit address, word size 16 bits – 128K x 32bits 128K addresses = 17 bit address, word size 32 bits

21. RAM Ram "sticks" from chips Main memory : 1+ sticks

22. Simple memory 8 chips, each with 4 addresses 32 possible address – Each number = address of byte

23. Simple memory 32 = 2 5 = 5 bit addresses

24. Simple memory 32 = 2 5 = 5 bit addresses 8 chips = 2 3 = 3 bits to pick chip 4 address per chip = 2 2 = 2 bits for offest

25. Simple memory AddressModule Number Byte on Module DecBinary 10000101 140111032 201010050 70011113 311111173

26. Simple memory High-Order Interleaving Low-Order Interleaving

27. Low-Order Address High order bits now byte on module AddressByte on Module Module Number DecBinary 10000101 140111016 201010024

28. Bigger Scale 2GBytes byte addressable memory made from 128M x 32 bit chips – How many chips? – What do addresses look like?

29. Bigger Scale Each chip has word size 32, 128M addresses: = 128M x 32 bits = 128M x 4 bytes = 512MB Total : 2GB = 2 1 * 2 30 = 2 31 Per Chip : 512MB = 2 9 * 2 20 = 2 29 2 31 / 2 29 = 2 2 = 4 Four 128M x 32 chips for 2GB byte addressable

30. Bigger Scale Addresses: – 2GBytes = 2 1 * 2 30 = 2 31 total addresses 31 bits – Each chip: 512MBytes = 2 9 * 2 20 = 2 29 addresses 29 bits – Chip select: 4 chips = 2 2 2 bits

31. Bigger Scale 31 bit address – 2 bit chip select – 29 bits for offset on chip ChipByte Bits 30-29Bits 28-0 2  4 Decoder29  512M Decoder