1. ITRS Emerging Logic Device working group George Bourianoff, Intel Potsdam, Germany April 10, 2011 12011 ERD Meeting Potsdam, Germany

2. Outline Overview –Large change from last year –Strong involvement with NRI Review 2009 and 2011 Tables Review transition Table issues and observations April 10, 201122011 ERD Meeting Potsdam, Germany

3. 2011 R1 Logic Transition Table April 10, 201132011 ERD Meeting Potsdam, Germany

4. 2009 Table 1 MOSFETs Extending the Channel of MOSFETs to the End of the roadmap Table ERD7b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices DeviceFET [A]Tunnel FET Negative Cg FETSpin Transistor Typical example devicesSi CMOS All Si tunnel FET Strained Ge or III-V source tunnel FET, Heterostructure tunnel FET I-MOSFerroelectric FET [H], [I] Spin FET [K] Single Electron Transistor MEMS Spin MOSFET bCell Size Projected100 nm 20 nm [A] 100 nm100 nm [same as CMOS] 100 nm 40 nm [O] 100 nm [X} (spatial pitch) [B]for spin MOSFET [L] Demonstrated590 nm Demonstrated: 70 nm, 100nm [B,C] Unknown ~1  m (channel length) ~200 nm [P,Q] 900 nm 2000 nmfor Spin FET[M] Density (device/cm 2 ) Projected1.00E+10 Not known: 1E10[same as CMOS] [I] ~1E10 6.00E+10 1.00E+10 channel length scalable down to 20nm [D] 1.00E+10for spin MOSFET [L] Demonstrated2.80E+08~1E102.50E+07UnknownNot investigated~2E9 1 /cm**2 W2 Switch Speed Projected12 THzNot known Unknown Limited by the ferroelectric response time, depends on the ferroelectric material ~10 THz or less 10 THz [R] 1 GHz [Y] Identical to CMOSFET- with Ge, SiGe [E],[F],[G] for spin MOSFET [N]] Demonstrated1.5 THz Si/Ge/InAs tunneling source: not known N/A 30GHz 2 THz [S] 0.18 GHz [Z] 1GHz/1THz/3THz [A] for Spin FET[M] Circuit Speed Projected61 GHzNot known Unknown Limited by the ferroelectric response time, depends on the ferroelectric material ~10GHz or less 2 GHz [O] 1 GHz Identical to CMOSFET- with Ge, SiGe [E],[F],[G] for spin MOSFET [M] Demonstrated5.6 GHz Not known: N/ANot investigated1 MHz [T].18 GHz will depend on the source material used not known Switching Energy, J Projected3.00E-18Not known unknown 1E-17-1E-181×10 –18 [O] 5E -17 J [A1,A2] Identical to CMOSFET- with Ge, SiGe [E],[F],[G] for spin MOSFET [M]][>1.5×10 –17 ] [U] Demonstrated1.00E-16 Si/Ge/InAs tunneling source: N/ANot investigated 8×10 –17 [V] 90/90/3000E-18 [>1.3×10 –14 ] [W] J/um at VDD=0.5V, L=20nm [A] not known Binary Throughput, GBit/ns/cm 2 Projected238Not knownnot knownNot known ~200 10 April 10, 201142011 ERD Meeting Potsdam, Germany

5. DeviceFET [A] Nanowire FETsTunnel FETN channel MOSFETSP channel MOSFETs Typical example devicesSi CMOSCNT FETGraphene Nanoribbon FET All Si, Ge and silicide source, VLS nanowire InP (N) Ge(N)GaSb(P) Cell SizeProjected100 nm 20 nmTBD (spatial pitch) [B]Demonstrated590 nm 1.4 μ m[G]1.4 μ m[G]] sub 60 nm[A],60nm[B]TBD Density (device/cm 2 ) Projected1.00E+10 channel down to 20nm [C, D]: 1E10 TBD Demonstrated2.80E+085.10E+07 not known TBD Switch Speed Projected12 THz7 THz [H] Si /InAs TFET: 60GHz/3THz [E] TBD Demonstrated1.5 THz300GHz [I] not known TBD Circuit Speed Projected61 GHznot known Si/InAs TFET inverter: 20GHz, 1THz [E] TBD Demonstrated5.6 GHz22 kHz [J] not known TBD Switching Energy, J Projected3.00E-18not known CGG*VDD^2 (J/um) < 2E- 17 [F] TBD Demonstrated1.00E-16not known CGG*VDD^2 (J/um) =1E-16 [F] TBD Binary Throughput, GBit/ns/cm 2 Projected238not known TBD Demonstrated1.6not known TBD Operational TemperatureRT TBD Material ChallengesSiCNT density, contacts dialectrics, substrates, in situ mobility, contactsnot known TBD Research Activity [AD] not knownTBD 2011 Table 1 MOSFETS: Extending MOSFETs to the End of the Roadmap. April 10, 201152011 ERD Meeting Potsdam, Germany

6. 2009 Table 2 Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices April 10, 201162011 ERD Meeting Potsdam, Germany

7. DeviceFET [A] Spin FET and Spin MOSFET I MOSMEMsAtomic Switch Electronic phase transition P/N Junction Typical example devicesSi CMOSSpin MOSFET Si elevated SixGe1-x, Siy C1-y BDD device [1}, [2] bCell Size Projected100 nm 100nm [L] 100 nm [I1) 1oo nm (spatial pitch) [B] Demonstrated590 nmNot known 2um [I2], 60nm [I3] Density (device/cm 2 ) Projected1.00E+101E10[L] 1.o E+10 1.00E+10 Demonstrated2.80E+08Not known2.00E+07 Switch Speed Projected12 THz10 THz or less [M] 76 TH 0.1THz for Ioff=0.1uA/um, Lg=50nm [I4] Demonstrated1.5 THz Not known Circuit Speed Projected61 GHz10 GHz or less [M] Similar with Si CMOS Inverter, Lg=130nm, 50GHz [I5] 3.29 THz Demonstrated5.6 GHz Not known Switching Energy, J Projected3.00E-18~1E-17 [M] Larger than CMOS, unscalable BV [I6] 3.28E-17 Demonstrated1.00E-16 Not known Binary Throughput, GBit/ns/cm 2 Projected238not known 32900 2011 Table 2 Table ERD7b Charge based Beyond CMOS: Non-Conventional FETs and other Charge- based information carrier devices April 10, 201172011 ERD Meeting Potsdam, Germany

8. 2011 Table 2Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices April 10, 201182011 ERD Meeting Potsdam, Germany

9. 2009 Table 3 Non-FET, Non Charge-based ‘Beyond CMOS’ devises April 10, 201192011 ERD Meeting Potsdam, Germany

10. Spin Wave DevicesNanomagnetic LogicExcitonic FETBISFETFerroelectric Neg CgSpin Torque Majority GateAll Spin Logic State Variable Magnetization Excitonic insulator in the off- state, Conventional conductor in the on-state existance or not of superfluid excitonic condensate Charge[8]Spin wave frequency Spin/Magnetization [13] Function Boolean Logic Gate enables transition from the "conventional" device on-state into the excitonic insulating state by tuning the electron and hole density to become identical Gate controled negative differnential resistance (NDR) Three terminal switch[9] Performs the majority logic gate operation via phase locking of spin torque oscillators with a common ferromagnetic nanowire free layer spin wave bus [A, B] Non-linear Class—Example Majority GateSteep subthreshold slope device superconducting, pseudospin device—BiSFET Median function [14] Architecture Systolic/pipelinedConventional CMOSMorphic MOSFET[9] A ferromagnetic nanowire spin wave bus on a metallic substrate with several injectors of spin-polarized current for spin-torque excitation of spin waves [C, D] Morphic Application Low power, non-volatile, radiation hard Device for low-power applications low power, high speed, general purpose logic Switch[9] Majority logic gate operation with spin waves [E] General purpose/Non volatile/Reconfigurable logic [17] Comments Compatible memory technology: MRAM While drag has been observed [1-4] and excitons have been detected in systems with spatially separated channels [5- 7], the transition to an excitonic insulator has not been observed. Extremely low power; 4-phase clocked power supply Drop in MOSFET repplacement with reduced Vdd[9] Development of this device will leverage the spin wave device development effort because spin torque provides energy-effieicnet excitation of spin waves High speed, low power and zero standby power Status Feasibility, CMOS compatible clocking experimentally demonstrated Experimental work to create this device is ongoing in my group Simulated proof of concept demonstrated[10,11,12] Phase locking of two spin torque oscillators via spin waves in the common free layer is demonstrated [A, B] Simulation / some low temperature experiments Material Issues MRAM/CMOS compatible We believe that graphene is ideally suited for this application because of the symmetry of the electron and hole dispersion Low defect paired graphene layers and compatible thin dielectrics, low resistance contacts integration of appropriate ferroelectric with semiconductors is needed[8,9,10,11,12] NiFe, Cu, Ru, IrMn, CoFe, MgO, CoFeB, Ta (a) Spin coherent channels with reduced electromigration. (b) Magnets with high aniostropy for low energy operation [15,16] 2011 Table 3: Non-FET, Non Charge-based ‘Beyond CMOS’ devises April 10, 2011102011 ERD Meeting Potsdam, Germany

11. 2011 R1 Logic Transition Table April 10, 2011112011 ERD Meeting Potsdam, Germany

12. # Decisions Made 1. Memory: ♦ Put Vertical MOSFET in the Memory Section. 2. Logic: ♦ Leave n-channel Ge and InP MOSFETs and p-channel GaSb MOSFETs in ERD/ERM ♦ The Tunnel FET should remain in the main Logic Tables and Section. ♦ Nanowire FET stays in ERD/ERM. ♦ Remove molecular from Logic Section – does not meet criteria ♦ Add MOTT-FET to the Logic Section ♦ Remove SET or move SET to the MtM Section ♦ Keep InP and Ge n-channel and GaSb p-channel MOSFETs in the Logic Section ♦ Add devices from NRI that meet the selection criteria ♦ Do not include Vertical MOSFET in Logic; keep/put in Memory Section. ♦ Change “Collective Spin Wave? to “Spin Wave”. ♦ Logic Working Group is: Shamik (Nanowires), Adrian (Tunnel FET),??(InP, Ge, GaSb), Jeff Welser (NRI Devices added), Jeff Kitun? ♦ Include the Spin Torque Majority Gate. ♦ Keep the Atomic Switch in Logic Tables (corrected Feb. 17, 2011) April 10, 2011122011 ERD Meeting Potsdam, Germany

13. Issues and observations Ownership for N channel Ge and InP MOSFETs Ownership for `P channel GaSb MOSFETs Ownership for atomic bridge Critical material challenges is not uniform 3 entries promised, 3 in question NRI benchmarking activity provides valuable input – would be useful of have similar input from other regions April 10, 2011132011 ERD Meeting Potsdam, Germany

14. year Beyond CMOS Elements ERD-WG in Japan Existing technologies New technologies Evolution of Extended CMOS April 10, 2011142011 ERD Meeting Potsdam, Germany