1. Unit 5 Lecture 2 Error Control Error Detection & Error Correction

2. Methods of error control Error control involves two basic methods: 1.error detection 2.error correction

3. Detection versus Correction The correction of errors is more difficult than the detection. In error detection, we are only looking to see if any error has occurred. The answer is a simple yes or no. We are not even interested in the number of corrupted bits. A single-bit error is the same for us as a burst error. In error correction, we need to know the exact number of bits that are corrupted and, more importantly, their location in the message.

4. Issues in detecting & correcting errors Redundancy Coding Block Coding Convolution coding

5. 10.5Redundancy The Redundancy is a central concept in detecting or correcting errors. To be able to detect or correct errors, we need to send some extra bits with our data. These redundant bits are added by the sender and removed by the receiver. Their presence allows the receiver to detect or correct corrupted bits. Extra added bits are called redundant because they are having no value in information and discarded as soon as the accuracy of transmission is determined.

6. Redundancy Figure

7. 10.7Coding Redundancy is achieved through various coding schemes. The sender adds redundant bits through a process that creates a relationship between the redundant bits and the actual data bits. The receiver checks the relationships between the two sets of bits to detect errors. The ratio of redundant bits to data bits and the robustness of the process are important factors in any coding scheme.

8. Four types of redundancy checks are used in data communication 1. Vertical redundancy check (VRC) ( also called as parity check) 2. Longitudinal redundancy check (LRC) 3. Cyclic redundancy check (CRC) 4. Checksum First three methods VRC, LRC & CRC are implemented at Physical layer The fourth checksum method is used primarily by upper layer like transport layer

9. Figure: Detection Methods

10. VRC The most common & the least expensive mechanism for error detection is the vertical redundancy check(VRC) This method is also called as parity check In this method a redundant bit, called a parity bit, is appended to every data unit so that the total number of 1s in the unit (including parity bit) becomes even.

11. Parity checking In parity checking method, an additional bit called parity bit added to each data word. The additional bit is so chosen that the weight of the code word thus formed is either even or odd All the code words of a code set have the same parity which is decided in advance.

12. VRC Figure

13. Even-parity concept

14. Even and odd parity bits. P : Parity bit Even Parity PData word 01001011 10010110 Odd Parity PData word 11001011 00010110

15. When a single error or an odd number of errors occurs during transmission, the parity of the code word changes. Parity of the code word is checked at the receiving end and violation of the parity rule indicate errors somewhere in the code word.

16. Error detection by change in parity Transmitted code word10010110Even parity Received code word (single error) 00010110Odd parity (Error is detected) Received code word (double error) 00011110Even parity (Error is not detected) In parity check, a parity bit is added to every data unit so that the total number of 1s is even (or odd for odd-parity).

17. Note:

18. Example 1 Suppose the sender wants to send the word world. In ASCII the five characters are coded as 1110111 1101111 1110010 1101100 1100100 The following shows the actual bits sent 11101110 11011110 11100100 11011000 11001001

19. Example 2 Now suppose the word world in Example 1 is received by the receiver without being corrupted in transmission. 11101110 11011110 11100100 11011000 11001001 The receiver counts the 1s in each character and comes up with even numbers (6, 6, 4, 4, 4). The data are accepted.

20. Example 3 Now suppose the word world in Example 1 is corrupted during transmission. 11111110 11011110 11101100 11011000 11001001 The receiver counts the 1s in each character and comes up with even and odd numbers (7, 6, 5, 4, 4). The receiver knows that the data are corrupted, discards them, and asks for retransmission.

21. Performance of VRC VRC can detect all single-bit errors. It can also detect burst errors as long as the total number of bits changed is odd (1, 3, 5, etc). Let’s say we have an even-parity data until where the total number of I’s including the parity bit, is 6: 1000111011. if any three bits change value, the resulting parity will be odd and the error will be detected : 1111111011:9, 0110111011:7, 1100010011:5 all odd.

22. The VRC checker would return a result of 1 and the data unit would be rejected. The same holds true for any odd number of errors. Suppose, however, that two bits of the data unit are changed: 1110111011:8, 1100011011:6, 1000011010:4. in each case the number of 1’s in the data unit is still even. The VRC checker will add them and return an even number although the data unit contains two errors.

23. VRC cannot detect errors where the total number of bits changed is even. If any two bits change in transmission, the changes cancel each other and the data unit will pass a parity check even though the data unit is damaged. The same holds true for any even number of errors. VRC can detect all single bit-single errors. It can detect burst errors only if the total number of errors in each data unit is odd.

24. HW implementation XOR GATE NOTGATE

26. VRC Generator/Parity Generator VRC Generator A VRC generator is a series of XOR gates. The number of gates in the generator is one less than the number of bits in the data unit. The final result is the even- parity bit. Figure shows how this process works. To generate an odd-parity bit, the output of the last XOR gate is passed through a NOT gate.

27. VRC Checker/Parity Checker The VRC checker at the receiving end has one extra XOR gate to accommodate the parity bit. The process is also the same: the output of each XOR gate is passed to the next XOR gate, where it is added to the next bit in the data unit. As with parity generation, an odd-parity checker is identical to an even-parity checker except for the addition of a NOT gate after the last XOR gate. If the final output is 0, the transmission is assumed to the intact, the parity bit is dropped, and the data are accepted. If the output is 1, the data are rejected. Figure shows an even-parity VRC checker.

28. Longitudinal Redundancy Check (LRC) In Longitudinal Redundancy Check (LRC), a block of bits is organized in a table (rows and columns) For example, instead of sending a block of 32 bits, We organize them in a table made of four rows and eight columns, as shown in figure, We then calculate the parity bit for each column and create a new row of eight bits, which are the parity bits for the whole block.

30. LRC Figure

31. In Longitudinal Redundancy Check (LRC), a block of bits is divided into rows and redundant rows of bits is added to the whole block

32. Example LRC Suppose the following block is sent 10101001 00111001 11011101 11100111 10101010 (LRC) However, it is bit by a burst noise of length and some bits are corrupted 10100011 10001001 11011101 11100111 10101010 (LRC)

33. When the receiver checks the LRC, some of the bits do not follow the even-parity rule and the whole block is discarded (the non matching bits are shown in bold). 10100011 10001001 11011101 11100111 10101010 (LRC)

34. Performance of LRC LRC increases the likelihood of detecting burst errors. As we showed in the previous example, an LRC of n bits can easily detect a burst error of n bits. A burst error of more than n bits is also detected by LRC with a very high probability. There is, however, one pattern of errors that remains elusive. If two bits in one data unit are damaged and two bits in exactly the same positions in another data unit are also damaged, the LRC checker will not detect an error. Consider, for example, two data units : 11110000 and 11000011. If the first and last bits in each of them are changed, making the data units read 01110001 and 01000010, the errors cannot be detected by LRC.

35. HW implementation of LRC LRC Generator Figure shows how the LRC is calculated. The least significant bits are added together and their parity found; then the second bits are added and their parity found, and so on. The final bit of the LRC is both the parity bit for the LRC data unit itself and the parity bit for all the VRC parity bits in the block.

36. LRC Checker An LRC checker works like an LRC generator, but we need extra XOR gates, Figure shows an LRC checker.

37. Block Parity Two Dimensional Parity check When a large no of binary words are being transmitted or received in succession, the resulting collection of bits is considered as block of data & is represented in rows & columns. The parity bit is produced for each row & column of such block of data It uses the concept of VRC & LRC together

38. VRC and LRC

39. Example of Block Parity/Two Dimensional Parity

40. Two-dimensional parity