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EE3A1 Computer Hardware and Digital Design Lecture 6 supplement Common misunderstandings about VHDL processes.

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Presentation on theme: "EE3A1 Computer Hardware and Digital Design Lecture 6 supplement Common misunderstandings about VHDL processes."— Presentation transcript:

1 EE3A1 Computer Hardware and Digital Design Lecture 6 supplement Common misunderstandings about VHDL processes

2 Introduction  How VHDL works inside processes  It’s sequential, but …

3 Sequential programming languages  Example in C, C++, Java:  Initially a=“0000”, b=“0001” and c=“0010”. { b = c; a = b; } First this statement runs Now a=“0000”, b=“0010” and c=“0010”. Then this statement runs Now a=“0010”, b=“0010” and c=“0010”.

4 Behaviour of VHDL processes  VHDL counterpart  Initially a=“0000”, b=“0001” and c=“0010”. process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Process is entered: values of a, b, c are frozen When clock changes and put onto queue as future value for a Current value of b is read: 0001 On leaving process: a, b, c are unfrozen They receive their new values from queue a=“0001”, b=“0010” and c=“0010”. and put onto queue as future value for b Current value of c is read: 0010

5 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value000000010010 Future value

6 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value000000010010 Future value

7 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value000000010010 Future value

8 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value000000010010 Future value

9 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value000000010010 Future value0010

10 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value000000010010 Future value00010010

11 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value000000010010 Future value00010010

12 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value00010010 Future value

13 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Value of c has copied to b, but not to a Different from sequential programming languages abc Current value00010010 Future value

14 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; What happens if we let it run one more clock cycle? abc Current value00010010 Future value

15 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value00010010 Future value

16 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value00010010 Future value

17 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value00010010 Future value

18 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value00010010 Future value

19 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value00010010 Future value0010

20 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value00010010 Future value0010

21 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Values frozenabc Current value00010010 Future value0010

22 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; abc Current value0010 Future value

23 Behaviour of VHDL processes process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Value of c takes two clock cycles (two runs of the process) to reach a abc Current value0010 Future value

24 Effect of statement order  In C, C++ or Java these are completely different: { b = c; a = b; } { a = b; b = c; }  Suppose initially a=”0000”, b=”0001” and c=”0010”.  Left-hand code gives u a=”0010”, b=”0010” and c=”0010”.  Right-hand code gives u a=”0001”, b=”0010” and c=”0010”.

25 Effect of statement order  These VHDL codes are identical in effect: process (clk) begin if (rising_edge(clk)) then b <= c; a <= b; end if; end process; process (clk) begin if (rising_edge(clk)) then a <= b; b <= c; end if; end process;  Statements b<=c and a<=b do run in a different order.  But all signals are frozen during execution  Update takes place on exit from process

26 What is corresponding hardware? process (clk) begin if ( rising_edge(clk) ) then b <= c; a <= b; end if; end process; Shift register or Simple pipeline

27 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; Wrong! Circuit outputs change whenever input changes Put all inputs in sensitivity list

28 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 0 0 0 0 0 0 Suppose x changes 0 to 1

29 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

30 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

31 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

32 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

33 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process finishes execution: Update all values

34 Using Processes for Combinational Logic PROCESS (x, y, cin) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Final answer for sum is wrong Should be 1

35 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; Correct! Circuit outputs change whenever input changes, or whenever n1 changes Put inputs and n1 in sensitivity list

36 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 0 0 0 0 0 0 Suppose x changes 0 to 1

37 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

38 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

39 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

40 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

41 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 0 0 New value 0 New value will be 0 (0 XOR 0) New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process finishes execution: Update all values

42 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 Suppose x changes 0 to 1 n1 has just changed Process re-runs

43 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

44 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

45 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

46 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process executes with all LHS values frozen

47 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 0 0 1 0 New value 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process finishes execution: Update all values

48 Using Processes Correctly PROCESS (x, y, cin, n1) BEGIN n1 <= x XOR y; sum <= cin XOR n1; cout <= ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END PROCESS; 1 0 1 0 1 0 New value 0 New value will be 1 (1 XOR 0) Suppose x changes 0 to 1 Process finishes execution: Update all values

49 Rules of Combinational Logic  For combinational logic, sensitivity list should contain u All inputs u All internal nodes

50 Question  Which give the correct functionality? a: PROCESS (a,b,c,d) BEGIN d <= a AND b; e <= c OR d; END PROCESS; b: PROCESS (a,b,c) BEGIN e <= c OR ( a AND b ); END PROCESS; d: PROCESS (a,b,c) BEGIN d <= a AND b; e <= c OR d; END PROCESS; c: PROCESS (a,b,c,d) BEGIN e <= c OR d; d <= a AND b; END PROCESS;

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