1. NC STATE UNIVERSITY Tapping ZettaRAM™ for Low-Power Memory Systems Center for Embedded Systems Research (CESR) Department of Electrical & Computer Engineering North Carolina State University Ravi K. Venkatesan, Ahmed S. AL-Zawawi, Eric Rotenberg

2. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 2 ZettaRAM  New memory from ZettaCore™ –Genesis in DARPA Moletronics –Molecule stores 1 charge  Long-term –1 molecule = 1 bit  Near-Term –Use molecules in aggregate –Replace DRAM capacitor Porphyrin Molecule ZettaRAM Molecular Capacitor linker

3. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 3 Benefits  Manufacturing –Self–assembly –High charge density –Precise control of molecules’ attributes  Other unusual properties?  Architectural opportunities? cost-effectively scale DRAM density flexibly control density, performance, energy

4. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 4 DRAM 0 1 V DD V BL 0% 100% charge V BL 0/1? V BL Bit Line DRAM capacitor 0

5. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 5 ZettaRAM Very low-power memory 0 1 0 V DD V BL 0% 100% charge V BL Bit Line ZettaRAM capacitor V ox

6. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 6 But… Speed-energy tradeoff 0 1 V DD V slow 0% 100% charge V slow Bit Line ZettaRAM capacitor V ox V fast 0

7. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 7 SPICE Results  SPICE model based on Butler-Volmer equation 1.0V: 166 ns 1.1V: 29 ns 1.2V: 9 ns

8. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 8 ZettaRAM : Performance-Energy Tradeoff Bitline energy w.r.t. DRAM Execution time w.r.t. DRAM

9. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 9 Goal  ZettaRAM offers novel performance-energy tradeoff –DRAM inflexible  Architectural techniques to manage main memory –Tap the energy-savings potential –Minimize performance degradation

10. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 10 Source of Bitline Activity Proc L2 $ row buffer hit row buffer Z-RAM row buffer miss No bitline activity bitline activity close old page open new page service request fetch cache block OR writeback cache block 1 23 2 4

11. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 11 Row Buffer Miss Rates  L2 writebacks account for 80% of bitline activity Most of energy consumption

12. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 12 Ideal Combination of Factors Target writebacks – Most of energy savings potential – Not performance-critical Hybrid Policy critical fetches V fast (high energy) non-critical writebacks V slow (low energy)

13. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 13 Hybrid Policy V fast V slow Proc L2 $ row buffer Z-RAM row buffer miss fetch cache block writeback cache block

14. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 14 Hybrid Policy Bitline energy w.r.t. DRAM Execution time w.r.t. DRAM Always fast F: 1.2 V WB: 1.2 V Always slow F: 1.0 V WB: 1.0 V Hybrid F: 1.2 V WB: 1.0 V Always fast F: 1.2 V WB: 1.2 V Always slow F: 1.0 V WB: 1.0 V Hybrid F: 1.2 V WB: 1.0 V

15. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 15 Eliminating Residual Slowdown  Residual 10% slowdown –Delayed writebacks occupy queues in memory controller –Eventually stalls processor (indirectly)  Tolerating delayed writebacks –Large buffers with access reordering –L2-cache eager writeback [Lee et al., MICRO33, 2000]

16. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 16 Large Buffers with Access Reordering  Enlarging queue increases –Cost: each entry contains cache block –Complexity: fetches that bypass writebacks must first search queue for read-after-write hazards 4 8 16 32 64 Queue Size Bitline energy w.r.t. DRAMExecution time w.r.t. DRAM Queue Size 4 8 16 32 64

17. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 17 block P L2 Cache Eager Writeback L2 cache Memory Processor miss in L2 cache fetch block Y fetched block Y clean block A block H block Q block W block F dirty load/store to block Y eager writeback block P block P LRU block Y

18. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 18 De-clustering L2 writeback requests Hybrid policy with 4 queue entries Hybrid policy with 4 queue entries in conjunction with eager writeback

19. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 19 Hybrid Policy + Eager Writeback in L2 cache Bitline energy w.r.t. DRAM Execution time w.r.t. DRAM 2 4 16 Queue Size 2 4 16 Queue Size

20. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 20 Conclusions  Molecular capacitor unique –Functional with arbitrarily small voltage swings –Speed is voltage dependent  Intelligently managing ZettaRAM –Hybrid policy –Eager writeback s ynergistic with ZettaRAM  Results –34% energy savings (out of 41% with uniformly slow writes) –Less than 1% performance degradation

21. NC STATE UNIVERSITY Ravi Venkatesan © 2005 HPCA-11 02/14/2005 21 Thank You Questions ?!? oThe ZettaRAM™ mark is a trademark of ZettaCore Inc oThe ZettaCore™ mark is a trademark of ZettaCore Inc Thank You Questions ?!? oThe ZettaRAM™ mark is a trademark of ZettaCore Inc oThe ZettaCore™ mark is a trademark of ZettaCore Inc