1. LSST Electronics Review – BNL, January 25-26 20121 LSST Electronics Review BNL January 25-26 2012 Electronics Development Plan Goals and Plans for 2012-13 R. Van Berg Electronics Mini-Review January 26 th, 2012

2. LSST Electronics Review – BNL, January 25-26 20122 Outline – VST Goals and Plans for 2012-13 Phase I –Analog performance –Digital performance –CCD drive/read performance Phase II –Analog performance –Digital performance –CCD drive/read performance –Environmental and contamination performance –Mechanical compatibility –Process development Phase III –Preproduction version –Full performance and compatibility check –Process finalization –Last chance to find problems before production

3. LSST Electronics Review – BNL, January 25-26 20123 Phase I – Analog Performance Noise –Inherent noise from ASPIC – DiffAmp – ADC chain –System noise from power (PSRR, inductive pickup, capacitive pickup, ….) –System noise from clock drive (SCC version) –Variations during a scan line Crosstalk –Geographic pickup (nearest neighbor channels FEB or BEB) –Time dependent (charge soak, insufficient clear time, ….) Dynamic range –17 Bits of ADC (or should we offset to get 18?) –90,000 e full well (or a lot more??) –2 bits of noise digitization Timing dependencies –Integration time –Reset / clear times –Etc. Note – all these lists are incomplete…

4. LSST Electronics Review – BNL, January 25-26 20124 Phase I – Digital Performance Data Rates –Backplane BER –Movement from backplane to Source Communication Interface (SCI) –Off of RCC to Optical Transition Module and beyond –Margins –Temperature effects – any at -40?? SPI Interfaces on BEB (and FEB eventually) –Rates –Interference with analog? –Command structure and efficiency

5. LSST Electronics Review – BNL, January 25-26 20125 Phase I – CCD Performance Interface to CCD emulator –Set up timings –Learn to move and interpret images –Look for 2D crosstalk patterns Interface to CCD –Bias and control voltage setup –Sequencing of voltages (CCD specific) –Protection against damage – what cases for each device are dangerous (if any)? –Clock voltages –Clock timing –Compare optima with ITL (and other) controller optima (should be similar, but??)

6. LSST Electronics Review – BNL, January 25-26 20126 Phase II – Analog Performance Noise –Inherent noise from ASPIC – DiffAmp – ADC chain –System noise from power (PSRR, inductive pickup, capacitive pickup, ….) –System noise from clock drive (CABAC) –System noise from SPI control operation –Variations during a scan line Crosstalk –Geographic pickup (nearest neighbor channels FEB or BEB) –Time dependent (charge soak, insufficient clear time, ….) Dynamic range –17 Bits of ADC (or should we offset to get 18?) –90,000 e full well (or a lot more??) – APIC gain adjustment –2 bits of noise digitization Timing dependencies –Integration time –Reset / clear times

7. LSST Electronics Review – BNL, January 25-26 20127 Phase II – Digital Performance Data Rates –ADC-RCM connections –Movement FPGA input to Source Communication Interface (SCI) –Off of RCC to Optical Transition Module and beyond –Margins –Temperature effects – any at -40?? SPI Interfaces on BEB and FEB –Rates –Interference with analog? –Interference one to another –Command structure and efficiency

8. LSST Electronics Review – BNL, January 25-26 20128 Phase II – CCD Drive / Read Performance Repeat Emulator setup and readout with new hardware Setup for E2V device –Protection and power sequencing –Timing optimization study –Image analysis –Optical input Crosstalk Noise Setup for ITL/STA device –Protection and power sequencing –Timing optimization study –Image analysis –Optical input Crosstalk Noise

9. LSST Electronics Review – BNL, January 25-26 20129 Phase II – Environmental and Contamination Performance Environmental –Hot carrier effects testing with full FEBs (high duty cycle) –CTE stress testing with boards assembled by target house with target process –Interconnect Stress Testing –Stress stand alone and assembled in FEC Contamination Testing –FEB and RCC treated separately –With Parylene C (without??) –Variations on cleaning and coating processes –Different candidate board materials

10. LSST Electronics Review – BNL, January 25-26 201210 Phase II – Mechanical Compatibility FEC piece fit –Cage sides –Cu clamp bars FEC assembly sequence(s) –Assembly to RSA –Cabling (CCDs and heaters and sensors on RSA) –Assembly to Cryoplate –Cabling to RCC –Assembly to Cold Plate Thermal impedances –Thermal tests (with dummy heaters or chips?) –Temp variation across board(s) –Variation board to board –Variation with clamp forces –Variation with materials (e.g. gold plating or??)

11. LSST Electronics Review – BNL, January 25-26 201211 Phase II - Process Development Part selection –Electrical properties –Reliability –Thermal properties Board materials –Thermal properties –Outgassing / contamination –Ease of assembly and repair Board assembly techniques –Leaded soldering –Cleaning –Testing – do we test then clean and coat and bag or two cycles of cleaning? –Cleaning methods (before and after Parylene application) –Baking –Coating –Reliability effects, if any

12. LSST Electronics Review – BNL, January 25-26 201212 Phase III – Preproduction Verification Electrical and mechanical verification –Bench tests for electrical performance –Assembly and fit tests for mechanics – one and multi RTMs –Metrology at BNL (and SLAC?) Operational tests –Full raft operation in cold Readout of multiple CCDs (9?) Thermal measure and control Meta data collection Configuration –Multi raft operation TCM JTAG configuration Readout Thermal control

13. LSST Electronics Review – BNL, January 25-26 201213 Phase III – Process Finalization Part selection and verification review Board material review Board assembly review Board cleaning review Board coating review Board test review Board rework review Board storage review Database (travelers) finalization and review Sign off on process plan Prepare for board production

14. End of Presentation