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A non-volatile Flip-Flop in Magnetic FPGA chip W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny Design and Test of Integrated Systems in Nanoscale.

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Presentation on theme: "A non-volatile Flip-Flop in Magnetic FPGA chip W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny Design and Test of Integrated Systems in Nanoscale."— Presentation transcript:

1 A non-volatile Flip-Flop in Magnetic FPGA chip W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny Design and Test of Integrated Systems in Nanoscale Technology, pp.323-326, 2006 指導老師 : 魏凱城 老師 學 生 : 蕭荃泰 日 期 : 97 年 4 月 14 日 彰化師範大學積體電路設計研究所

2 Outline  Abstract  Magnetic Flip-Flop  Magnetic Standard Non-Volatile Flip-Flop  MSFlip-Flop Simulation  Conclusion

3 Abstract  The propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed.  This flip-flop is based on MRAM (Magnetic RAM) technology on standard CMOS.  In this non-volatile flip-flop design, we use Magnetic Tunnel Junctions (MTJ) as storage element.  In this paper, a magnetic flip-flop is proposed to make the FPGA circuit completely non-volatile.

4 Magnetic Flip-Flop Fig1. the position of MTJs  Magnetic tunnel junction (MTJ) structure consisting of two ferromagnetic metals separated by a thin insulating layer.

5 Fig3. Magnetic Flip-Flop structuresFig2. SRAM based Master-Slave Flip-Flop structure

6 Fig4. schema of SRAM based sense amplifier

7 Fig5. Magnetic writing circuits 0 0 0 1 1 0 1 1

8 The simulation of magnetic Flip-Flop

9 Fig6. (a) Magnetic Standard mixed Flip-Flop schema (b) Magnetic Standard mixed Flip-Flop symbol (a) (b) Magnetic Standard Non-Volatile Flip-Flop

10 MSFlip-Flop Simulation  In the magnetic-standard flip-flop simulation, the low frequency control signal “ NW ” is 10 KHz, the clock frequency is 500MHz and the input frequency is 250MHz.  130nm technologies have been used for the CMOS part, and a complete simulation model has been developed by CEA for the magnetic part.

11 Fig7. The simulation results of magnetic standard non-volatile Flip-Flop. The last Data saved in MTJ is ‘ 1 ’

12 Fig8. The simulation results of magnetic standard non-volatile Flip-Flop. The last Data saved in MTJ is ‘ 0 ’

13 The flip-flop keeps the non-volatility of 1/X times (X is the ratio of processing frequency and the low, user defined frequency)

14 Conclusion  We proposed this new architecture of Magnetic Standard flip-flop which features simultaneously non-volatility, high speed and low power dissipation.  This flip-flop can also be used to replace all the registers in SOC (System-on-chip) then makes these chips non-volatile and secure.

15 The end


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