1. Diploma Project Real Time Motion Estimation on HDTV Video Streams (using the Xilinx FPGA) Supervisor :Averena L.I. Student:Das Samarjit

2. Introduction In this project I estimate the motion on HDTV video stream using the fastest motion estimation Algorithm with the FPGA of Xilinx Technology. I also implemented the motion estimation Algorithm to compensate the video frame to achieve better quality with lowest power consumption and flexible platform. Finally I generated the VHDL code for the Data processing unit for it to be implemented inside the FPGA architecture to obtain optimum performance.

3. Motion Estimation Algorithm Frame differencing method. Vector quantization method

4. Hybrid Video Encoding Simplified MPEG-1 Encoder

5. Hybrid Video Decoding Simplified MPEG-1 Decoder

6. Motion Estimation (Dominant Algorithm) Computational Power Distribution (for HDTV Tools)

7. Principals of Block Matching Motion Estimation Block Matching Algorithm

8. Block Matching Process-i

9. Block Matching Process-ii Block Matching Algorithm

10. Classification of Motion Estimation Gradient Based Motion Estimation(For Image sequence analysis). Pel-Recursive Motion Estimation(For Image Sequence coding). Block Matching Motion estimation(Best used for Video frame sequence coding). Frequency Domain Motion estimation (For video Encryption)

11. The Search Algorithm

12. The Tree step search Algorithm

13. The 2-D Logarithmic search Algorithm

14. Hexagonal Based search Algorithm

15. Motion Estimation Process in H.264/AVC A Fast Integer Pel search to estimate the motion vector. A Fast Integer Pel search to estimate the motion vector. A fractional pel search to determine the motion vector to a higher accuracy. A fractional pel search to determine the motion vector to a higher accuracy.

16. Block Diagram of H.264/AVC encoder

17. Motion Compensation with small block size

18. ¼ Pixel accurate motion compensation

19. Multiple Reference Picture motion compensation

20. Review of reconfigurable array architecture

21. The Reconfigurable instruction cell array architecture (RICA)

22. Design Flow for Algorithm implimentation on (RICA)

23. Flex WAFE Architecture with FIR Filter DPU Data stream communicators component (LMCs). Data stream communicators component (LMCs). Data stream processor component (DPUs). Data stream processor component (DPUs). Image Algorithm Dependent Global control (AC). Image Algorithm Dependent Global control (AC).

24. Flex WAFE Architecture with FIR Filter DPU

25. Flex WAFE Architecture building block LMC (here data is transferred reorganised and stored ). LMC (here data is transferred reorganised and stored ). DPU (It processes the data stream provided by the LMC). DPU (It processes the data stream provided by the LMC). AC (It reacts to the DPU and LMC via point to point connection to control the algorithm. AC (It reacts to the DPU and LMC via point to point connection to control the algorithm.

26. Comparison between DCT and DWT. Performance comparison of ZTE Wavelet coder

27. Compression Performance with respect of human visual system HVS A Bc

28. Test image ROI encoding A test image used to demonstrate the advantages of ROI coding

29. Implementation to FPGA

30. Compairing resources of a FPGA used DCT & DWT. (a) Xilinx virtex E-Series (b) Altera’s Apex 20KE series (a)(b)

31. Implimentation of Fast DCT&IDCT algorithm using various FPGA

32. Implementation on Xilinx FPGA

33. Performance of Xilinx FPGA

34. Overall Result Observing the result graph we depict that only Xilinx’s FPGA is able to process twice the rate required by the HDTV video stream – which is a remarkable achievement. Observing the result graph we depict that only Xilinx’s FPGA is able to process twice the rate required by the HDTV video stream – which is a remarkable achievement. By implementing a very fast DCT algorithm in Xilinx FPGA, I am able to process HDTV frames at a higher rate By implementing a very fast DCT algorithm in Xilinx FPGA, I am able to process HDTV frames at a higher rate So by implementing a very fast DCT algorithm (using the selected xilinx FPGA) I encrypt therefore encode the static image of video frame and then I implement the motion estimation algorithm to compensate the video frame to achieve better quality with lowest power consumption and time – therefore estimate the motion estimation on HDTV video streams in the real time using the Xilinx FPGA technology. So by implementing a very fast DCT algorithm (using the selected xilinx FPGA) I encrypt therefore encode the static image of video frame and then I implement the motion estimation algorithm to compensate the video frame to achieve better quality with lowest power consumption and time – therefore estimate the motion estimation on HDTV video streams in the real time using the Xilinx FPGA technology.