1. Chapter 11: Timer Subsystem Esteban Rodriguez-Marek Eastern Washington University Department of Engineering & Design

2. Chapter 11: Timer SUbsystem 2 of 65 Overview  The programmable timer subsystem of the 68HC11 can be used in any situation where an accurate time interval or measurement is required.  The heart of the subsystem is a free running counter (TCNT), which increments every integral number of clock cycles, depending on configuration.  Has three major functions: output compare input capture pulse accumulator

3. Chapter 11: Timer SUbsystem 3 of 65 Timer Subsytem Functions  Output compare – continually compares the stored value in an output compare register with the value in TCNT and when equal, asserts a change in output.  Input capture – used to measure pulse widths, frequency, speed, or any other quantity of a periodic signal.  Pulse accumulator – an 8-bit counter that can count input edges or measure pulse width (depending on the operating mode used).

4. Chapter 11: Timer SUbsystem 4 of 65 Registers  The timer subsystem has more registers than any other. They are:  Control Registers: TCTL1 – timer control register 1 (Output compare) TCTL2 – timer control register 2 (Input capture) TMSK1 – Main timer interrupt mask register 1 (output compare and input capture interrupt)

5. Chapter 11: Timer SUbsystem 5 of 65 Registers TMSK2 – Miscellaneous timer interrupt mask register 2 (Timer overflow and PA interrupts) PACTL – pulse accumulator control register OC1M – action mask register (dedicated to OC1) OC1D – action data register (dedicated to OC1)

6. Chapter 11: Timer SUbsystem 6 of 65 Registers  Data Registers: TCNT – timer counter register TIC1 through TIC3 – timer input capture registers 1, 2, and 3 TOC1 through TOC5 – timer output compare registers 1, 2, 3, 4, and 5 PACNT – pulse accumulator count register

7. Chapter 11: Timer SUbsystem 7 of 65 Registers  Status Registers: TFLG1 – Main timer interrupt flag register 1 (Output compare and input capture status flag) TFLG2 – Miscellaneous timer interrupt flag register 2 (Timer overflow and PA status flag)

8. Chapter 11: Timer SUbsystem 8 of 65 Pins  Each of the port A pins has a corresponding timer subsystem function.  Some have two possible functions.  If the timer function is not required (or not enabled), the corresponding port A pin can be used as a general purpose input or output pin depending on the specific pin.

9. Chapter 11: Timer SUbsystem 9 of 65 Pins  The following is a list of the port A pins and their designated timer functions: PA0 – input capture 3 (IC3) PA1 – input capture 2 (IC2) PA2 – input capture 1 (IC1) PA3 – output compare 5 or 1 (OC5/OC1) PA4 – output compare 4 or 1 (OC4/OC1) PA5 – output compare 3 or 1 (OC3/OC1) PA6 – output compare 2 or 1 (OC2/OC1) PA7 – pulse accumulator input or output compare 1 (PAI/OC1)

10. Chapter 11: Timer SUbsystem 10 of 65 MC68HC11E9 Block diagram

11. Chapter 11: Timer SUbsystem 11 of 65 Registers

12. Chapter 11: Timer SUbsystem 12 of 65 Registers

13. Chapter 11: Timer SUbsystem 13 of 65 The Free-Running Counter (TCNT)  The heart of the timer subsystem is the 16-bit timer counter register (TCNT) at address $100E, $100F.  For every set of clock pulses from the system clock (E), the register increments.  A program can read it at any time to get timing information.  The timer subsystem uses TCNT as a timing reference for most of its operations.  A program cannot write to the TCNT register. Only the system clock can change the register contents.

14. Chapter 11: Timer SUbsystem 14 of 65 The Free-Running Counter (TCNT)  The TCNT register is known as a free- running counter.  When the MCU is reset, register TCNT is also reset to zero. After this it increments at a fixed rate.  A prescaler is available to slow down the count rate by a factor of 1, 4, 8, or 16, depending upon the configuration.

15. Chapter 11: Timer SUbsystem 15 of 65 The Free-Running Counter (TCNT)  The prescaler can only be set once in a program, and it must be done within the first 64 system clock cycles.  Example: (Set prescaler for a factor of 8.) LDX#TMSK2;load address of TMSK2 register BCLR$00,X,$01;PR0 = 0 (Mmm ’ -> M) BSET$00,X,$02;PR1 = 1(M+mm -> M)

16. Chapter 11: Timer SUbsystem 16 of 65 The Free-Running Counter (TCNT)  After executing the instructions in the example above, the free-running counter (TCNT) will increment every eight clock cycles.  If the timer overflow interrupt enable bit (TOI) in register TMSK2 is set, an interrupt is also asserted.  If it is not set, the MCU will have to poll flag register TFLG2 to determine if an overflow has occurred.  An overflow occurs every time the register counts from $FFFF to $0000. This causes the timer overflow flag (TOF) in register TFLG2 to set.

17. Chapter 11: Timer SUbsystem 17 of 65 The Free-Running Counter (TCNT)

18. Chapter 11: Timer SUbsystem 18 of 65 Clearing Timer Flags  The flag bits in TFLG1 and TFLG2 are cleared by writing a 1 to the bit to be cleared.  ex) LDAA #80 ; sequence to clear TOF STAA TFLG2,X  ex) Suppose TFLG2 has $A0 BCLR TFLG2,X,$7F ; it will clear TOF ; (M(mm) ’  M)  ex) Suppose TFLG2 has $A0 BSET TFLG2,X,$80 ; (M+mm  M) - Bit7 and 5 in TFLAG will be cleared. - it is NOT a good way to clear flag bits.

19. Chapter 11: Timer SUbsystem 19 of 65 Output Compare  The output compare module can be used to generate waveforms such as square waves, variable-duty-cycle waves (PWM), and single pulses.  It can also trigger an execution sequence to begin at a specified time without generating an external output.  Output compare functions can be used to generate time delays that do not depend on executing a program loop a certain number of times.  An output compare function can generate repetitive signals such as a flashing light.  The ability to do PWM can be used to implement a simple D/A converter using only a few extra components.

20. Chapter 11: Timer SUbsystem 20 of 65 Output Compare Note : T0C1~TOC5 are at $1016 ~ $101F

21. Chapter 11: Timer SUbsystem 21 of 65 Output Compare Note : OC2 ~OC5 are assigned into PA6 ~ PA3 respectively.

22. Chapter 11: Timer SUbsystem 22 of 65 Sequence of Operations  There are five output compare functions and pins labeled OC1 to OC5.  Each has an associated 16-bit timer output compare register labeled TOC1 to TOC5 ($1016 to $101F), respectively.  A software instruction writes to the output compare register TOCx. When timer counter register TCNT counts up to the value stored in an output compare register, the MCU automatically sets the associated output compare flag (OcxF) in timer flag register TFLG1. This event is called a successful compare.

23. Chapter 11: Timer SUbsystem 23 of 65 Sequence of Operations  A successful compare will occur every time a match occurs between an output compare register and the counter register.  To write a value to an output register, use a double-byte instruction not two single-byte instructions. The latter could cause an erroneous compare.  Ex)LDX#TOC5 STD$00,X

24. Chapter 11: Timer SUbsystem 24 of 65 General Timer Software  Configure the control registers (and enable the subsystem)  Write to the data register if required.  Wait for a flag to set.  Clear the flag.  Read from or write to a data register as required.  Repeat if desired.

25. Chapter 11: Timer SUbsystem 25 of 65 One-Shot Pulse Example  This example will generate a pulse on pin OC2 that will be high for 10ms.  OC2 is also port A, pin 6 (PA6). Once a port A pin is configured for timer use, it cannot be used as a general-purpose pin.  Initially, the software sets pin PA6/OC2 high, which is the start of the pulse.  It then configures OC2 to drive the output low upon a successful compare.  Finally, the software writes a value to the output compare register TOC2 that represents the count that will be in TCNT at the end of the 10ms pulse.

26. Chapter 11: Timer SUbsystem 26 of 65 One-Shot Pulse Example  The value to be stored in TOC2 is calculated based on a 2MHz clock frequency and a timer prescale of 1.  Each clock cycle takes 0.5s so a 10ms pulse will require 20,000 cycles.  By the time TOC2 is written to, seventeen clock cycles have elapsed, meaning that the pulse has been on that long already.  Therefore, the value that should be written to TOC2 is the current value of TCNT plus 19,983 (20,000 – 17).

27. Chapter 11: Timer SUbsystem 27 of 65 One-Shot Pulse Example  An alternative way to initially set pin OC2 high is to use the timer compare force register (CFORC).  To force a compare, a one is written to the corresponding bit (FOCx) in the CFORC register. In this case, writing a one to FOC2 would force a compare action for OC2 (i.e., it makes OC2 changed even though a compare action is NOT performed).

28. Chapter 11: Timer SUbsystem 28 of 65 An example (1) * With E = 2 MHz and prescale = 1 * Drive one-shot high pulse for 10 ms * REMINDER, see template listing in Appendix D, Cross Assembly REGBASEQU$1000;Starting address for register ;block PORTAEQU$00 TCNTEQU$0E TOC2EQU$18 TCTL1EQU$20 TFLG1EQU$23 PWIDTHEQU20000

29. Chapter 11: Timer SUbsystem 29 of 65 An example (2) ORG$100 LDDTCNT,X ;prevent premature STDTOC2,X ;OC2 compare PULSEBSETPORTA,X $40 ;drive PA6/OC2 high (M+mm ->M) LDAA#$80 ;configure OC2 to drive output low STAATCTL1,X ;and disconnect other OCx's LDAA#$40 ;clear OC2F if set STAATFLG1,X LDDTCNT,X ;arm TOC2 for 10-ms trigger ADDD#PWIDTH-17 STDTOC2,X

30. Chapter 11: Timer SUbsystem 30 of 65 An example (3) PULSE1BRCLR TFLG1,X $40 PULSE1; ?Mmm=0 ;wait for trigger by *;polling for OC2F high *;now output OC2 low BCLRPORTA,X $40; Mmm ’ ->M ;clear latch for PA6 LDAA#$40;then clear OC2F STAATFLG1,X;before BCLRTCTL1,X $80;disconnecting OC2 BRA*;end for now

31. Chapter 11: Timer SUbsystem 31 of 65 Input Capture  An input capture function records the time (TCNT value) when an active transition occurred.  The active transition can be rising, falling, or either. This makes it useful for applications the require measuring the time between edges.  By using software, the MCU application program can calculate period, frequency, or any other related quantity such as speed.

32. Chapter 11: Timer SUbsystem 32 of 65 Input Capture  Referring to the diagram in next slide, it can be seen how the MCU software can find the waveform period by subtracting two successive edge times to find their difference.  It can then calculate frequency by dividing 1 by the period. Recall that frequency is the inverse of period.  The pulse width is the difference between the TCNT values when the edges occurred.

33. Chapter 11: Timer SUbsystem 33 of 65 Input Capture Note : IC3 ~IC1 are assigned into PA2 ~ PA0 respectively. TIC1~TIC3 are at $1010 ~ $1015.

34. Chapter 11: Timer SUbsystem 34 of 65 Sequence of Operations  When an edge is detected by the input capture pin, the value of the timer counter register (TCNT) is latched into the corresponding input capture register (TICx).  The function also sets the input capture flag (ICxF) in timer flag register 1 (TFLG1).  If the corresponding input capture interrupt enable bit (ICxI) in timer mask register 1 (TMSK1) is set, the detected edge also generates an interrupt.

35. Chapter 11: Timer SUbsystem 35 of 65 Sequence of Operations  Typically, the application program reads the value in the timer input capture register (TICx). It then clears flag ICxF so as to rearm itself to capture the next edge.  To detect whether a flag sets, the program can poll register TFLG1 or respond to an interrupt.

36. Chapter 11: Timer SUbsystem 36 of 65 An example for input capture operation (1) * Measure time between a rising and a falling edge on IC1. RISETIMEEQU$10 PULSEWIDTHEQU$12 ORG$100 LDAA#$10;config. to capture rising edge STAATCTL2,X LDAA#$04;clear flag IC1F if set STAATFLG1,X

37. Chapter 11: Timer SUbsystem 37 of 65 An example for input capture operation (2) * wait for rising edge POLLRISEBRCLRTFLG1,X $04 POLLRISE LDDTIC1,X;store the rise time STDRISETIME LDAA#$20;config. to capture falling edge STAATCTL2,X LDAA#$04;clear flag IC1F STAATFLG1,X * wait for falling edge POLLFALLBRCLRTFLG1,X $04 POLLFALL LDDTIC1,X;read the fall time SUBDRISETIME;width = fall - rise STDPULSEWIDTH;store width BRA*;stop here for now

38. Chapter 11: Timer SUbsystem 38 of 65 Pulse Accumulator  The pulse accumulator is an 8-bit counter that can count input edges or measure pulse width depending on the operating modes used.  It is not as accurate as the input capture functions for pulse-width measurement.

39. Chapter 11: Timer SUbsystem 39 of 65 Pulse Accumulator  However, the pulse accumulator can identify a wide pulse from a narrow pulse much more easily.  This makes it useful for decoding signals that use pulse width as part of their codes.

40. Chapter 11: Timer SUbsystem 40 of 65 Function Description  The pulse accumulator has one input pin (PAI) at port A pin PA7.  This is a bidirectional pin whose direction is configured by the data direction for PA7 bit (DDRA7) in the pulse accumulator control register (PACTL). DDRA 7 PAENPAMODPEDGEDDRA3I4/O5RTR1RTR0 $1026 PACTL

41. Chapter 11: Timer SUbsystem 41 of 65 Function Description  Normally, bit DDRA7 is zero when using the pulse accumulator. However, pin PA7 still drives the pulse accumulator if bit DDRA7 is set.  Control register PACTL has a pulse accumulator system enable bit (PAEN) which must be logic 1 in order to use the function.

42. Chapter 11: Timer SUbsystem 42 of 65 Function Description  Two other bits, pulse accumulator mode (PAMOD) and pulse accumulator edge control (PEDGE), establish the function ’ s operating modes. PAMOD=0 ; External event counting mode (pin acts as clock) PAMOD=1 ; Gated time accumulation mode (pin acts as clock enable for E divided by 64 clock. In this mode, PACNT is used as a timer. PACNT is incremented every 64 th E- clock cycle.)

43. Chapter 11: Timer SUbsystem 43 of 65 Function Description  The pulse accumulator count register (PACNT) can be read and written to. This means that the pulse accumulator can start counting from a preset count instead of zero.  The function also makes use of registers TFLG2 and TMSK2.

44. Chapter 11: Timer SUbsystem 44 of 65 Function Description  PA edge interrupt activates during a pulse edge.  Edge may be rising or falling: PEDGE = 0: Falling PEDGE = 1: Rising  Flag in Pulse Accumulator Input Edge Flag bit PAIF (TFLG2).  Enable bit for interrupt: PAII (TMSK2)

45. Chapter 11: Timer SUbsystem 45 of 65 Function Description  PA overflow interrupt activates whenever counter PACNT counts past $FF towards $00.  Pulse accumulator overflow bit (PAOVF) is in TFLG2.  Enable bit (PAOVI) is in TMSK2.

46. Chapter 11: Timer SUbsystem 46 of 65 Function Description Note : PAI is the pin, PA7

47. Chapter 11: Timer SUbsystem 47 of 65 Event Counting: Short counts  For counting short (i.e. <256) counts: Write 2 ’ s complement of preset number of edges to PACNT Ex. IF we want to count $18 edges, write $E8 ($18 = 00011000, two ’ s complement is 11101000 = $E8) When we reach $E8 + $17 = $FF one more count will set the PAOVF

48. Chapter 11: Timer SUbsystem 48 of 65 Example (short counts) (1) *INITPA: initializes PA for counting rising edges, * but does not enable interrupts INITPA pshx;preserves IX ldx#REGBBAS;point to reg blk bsetPACTL,X $50;PAEN=PEDGE=1 pulx;restore IX rts

49. Chapter 11: Timer SUbsystem 49 of 65 Example (short counts) (2) *CNTSPA: Counter (short) for PA. Loads PA function with preset and enables it for PAOVF overflow interrupt CNTSPA psha;preserve registers bclrtflg2,x$DF;Clear PAOVF (i.e. set it to 1) bsettmsk2,x $20; paovi = 1 nega;two ’ s complement staapacnt,x;store to PA counter cli;enable interrupts pula;restore regs rts

50. Chapter 11: Timer SUbsystem 50 of 65 Example (short counts) (3) *RPAOV: Interrupt handler for PA overflow RPAOV ldx#REGBAS bclrtmsk2,x $20; paovi = 0 bclrtflg2,x $DF; Clear PAOVF jsrgo_to_desired_subroutine rts

51. Chapter 11: Timer SUbsystem 51 of 65 Event Counting: Long counts  For counting long (i.e. >256) counts we need to keep track of PA overflows.  Ex: WE need to count $302 events. Store $FE (complement of $02) in PACNT. After 2 events have occurred, an overflow occurs. After that, we need to count 3 more overflows.  Use D reg: A will have multiples of 256, B will have remainder

52. Chapter 11: Timer SUbsystem 52 of 65 Example: Long counts (1) OVCNTrmb2; A value needs to ;be stored here to check how many ;events need to be counted org$180 ;Note INITPA from previous example ;is also used in this example

53. Chapter 11: Timer SUbsystem 53 of 65 Example: Long counts (2) CNTLPA ;Counter for long PA. Loads PA with preset values and ;enables it for overflow interrupt ;ACCD = preset, max = 65535 ;OVCNT = overflow count psha;preserve regs pshb bclrtflg2,x $DF;clear PAOVF bsettmsk2,x $20;paovi=1 tstb;test for remainder count beqNOINC;if none, skip inca inca

54. Chapter 11: Timer SUbsystem 54 of 65 Example: Long counts (3) NOINC negb;two ’ s complement remainter ; and store it in PACNT stabpacnt,x staaOVCNT;Store overflow count cli;enable interrupts pulb;restore regs pula rts

55. Chapter 11: Timer SUbsystem 55 of 65 Example: Long counts (4) RPAOV ;Handles PA overflow by decrementing count. Main app ;program checks if preset count is achieved by checking ;RAM variable OVCNT for zero ldx#regbas;point to regs bclrtflg2,x $DF;clear paovf decOVCNT;decr. overflow count rti

56. Chapter 11: Timer SUbsystem 56 of 65 Gated Time Accumulation  Set PAEN = PAMOD = 1  PA now counts up once every 64 clock cycles when PAI is active.  It does not count edges.  PEDGE specifies input that will inhibit time accumulation: PEDGE = 0: Counter will not increment if PAI is low PEDGE = 1: Counter will not increment if PAI is high

57. Chapter 11: Timer SUbsystem 57 of 65 Gated Time Accumulation  If PAI changes level, PACNT stops counting.  It will resume from the previous value when the input returns to enabling level.  Flag and interrupt bits work identically to event counting mode.

58. Chapter 11: Timer SUbsystem 58 of 65 Example: PW discriminator  Objective: Discriminate a narrow pulse from a wide one.  Do this by writing a value to PACNT that is halfway between narrow and wide pulse widths.  If narrow arrives, counter accumulates and trailing edge is detected before overflow occurs.  When wide arrives, counter accumulates and overflows before trailing edge.  Thus, if PAIF (edge flag) sets first, pulse was narrow.  If PAOVF (Overflow flag) sets first, pulse was wide.

59. Chapter 11: Timer SUbsystem 59 of 65 PW discriminator code (1)  Specs: Logic 1 = 0.25ms (narrow) Logic 0 = 0.5ms(wide)  Halfway = 0.375ms  PACNT counts every 64 cycles, or 32us.  375us/32us = roughy 12 = $0C  Two ’ s complement of $12 is $F4  System will use a low pulse for each bit (i.e. idle line is high).

60. Chapter 11: Timer SUbsystem 60 of 65 PW discriminator code (2) ORG $180 STBLKequ$20 ENDBLKequ $2F ;stblk and endblk: 1st and last add. of block ;where data is stored ;program will read data and store bits in the ;above locations

61. Chapter 11: Timer SUbsystem 61 of 65 PW discriminator code (3) INPA psha pshb pshx pshy;preserve regs ldy#STBLK;initialize pointer to data ldx#regbas;reg block

62. Chapter 11: Timer SUbsystem 62 of 65 PW discriminator code (4) ;config. PA in gated mode ldaa#%01110000 staapactl,x;low level enables accumulation ldaa#$30;enable local interrupts Staatmsk2,x Staatflg2,x;and clear flags if set Ldaa#$F4;preset pulse accumulator Staapacnt,x NEXTBYTE ldab#8;loop from 8:1 clr0,y;clear data byte

63. Chapter 11: Timer SUbsystem 63 of 65 PW discriminator code (5) NEXTBIT cli;enable interrupt and wait for wai;either interrupt to shift in a bit decb;decrease bit count bneNEXTBIT;until 8 bits shifted in iny;increase byte pointer cpy#ENDBLK;until last byte read bneNEXTBYTE sei;mask interrupts puly;recover registers pulx pulb Pula rts

64. Chapter 11: Timer SUbsystem 64 of 65 PW discriminator code (6) RPAO ;PA overflow handler ;if overflow occurred first, bit = 0 ldaa0,y;get old data byte clc;shift in a zero bit (clc = clear carry) rola;rotate carry bit in staa0,y;and store it WAIT1 ;inhibit rising edge interrupt brclrtflg2,x$10WAIT1 bclrtflg2,x$CF;clear flags PAOVF and PAIF ldaa#$F4;restore acc. preset staapacnt,x rti

65. Chapter 11: Timer SUbsystem 65 of 65 PW discriminator code (7) RPAIE ;PA edge detection handler ;if rising edge occurred first, bit = 1 ldaa0,y;get old data byte sec;shift in a one bit (sec = set carry) rola;rotate carry bit in staa0,y;and store it bclrtflg2,x$CF;clear flags PAOVF and PAIF ldaa#$F4;restore acc. preset staapacnt,x rts