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1 Modelling and Simulation of Ethernet Based Networked Mechanical Systems Department of Mechanical & Industrial Engineering Concordia University Control.

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Presentation on theme: "1 Modelling and Simulation of Ethernet Based Networked Mechanical Systems Department of Mechanical & Industrial Engineering Concordia University Control."— Presentation transcript:

1 1 Modelling and Simulation of Ethernet Based Networked Mechanical Systems Department of Mechanical & Industrial Engineering Concordia University Control and Information Systems (CIS) Laboratory Presented By : Vahid Shaker Supervisor : Dr. Brandon W. Gordon

2 2 Out Line Motivation Motivation Problem definition Problem definition Basics of Ethernet technology Basics of Ethernet technology Our approach Our approach S-Function simulation S-Function simulation Modelling of Ethernet components Modelling of Ethernet components Testing and verification Testing and verification Application to distributed simulation Application to distributed simulation Conclusion and future work Conclusion and future work

3 3 Motivation Need to predict the behavior of Ethernet networks combined with mechanical systems Need to predict the behavior of Ethernet networks combined with mechanical systems Main applications are design and analysis of Ethernet based distributed simulation and control systems Main applications are design and analysis of Ethernet based distributed simulation and control systems A modular modelling and simulation approach is needed A modular modelling and simulation approach is needed

4 4 Problem Definition To predict the overall time delay of transmitted packets To predict the overall time delay of transmitted packets Estimate the real-time performance of Ethernet / mechanical systems in different topologies Estimate the real-time performance of Ethernet / mechanical systems in different topologies

5 5 Basics of Ethernet Technology Ethernet uses a contention-based channel access method called CSMA/CD (Carrier Sense Multiple Access with Collision Detection) Ethernet uses a contention-based channel access method called CSMA/CD (Carrier Sense Multiple Access with Collision Detection) Half and full duplex modes Half and full duplex modes Ethernet frame structure Ethernet frame structure PreambleSFD I /G U/LDASA Length / Type Data / LLC FCS568484816 46 to 1500 32 32

6 6 Common Network Topologies Bus Star

7 7 Our Approach Develop FSM (Finite State Machine) models of : Develop FSM (Finite State Machine) models of : - Network Interface card (NIC) - Network Interface card (NIC) - Bus - Bus - Hub - Switch Implement the models using C++ functions Implement the models using C++ functions Individually test, run and debug each subsystem model Individually test, run and debug each subsystem model

8 8 Our Approach (Cont.) Encapsulate the codes using Simulink  Encapsulate the codes using Simulink  S-functions S-functions Individually test, run and debug each Individually test, run and debug each S-function S-function Interconnect the blocks in Simulink to arrange the appropriate model Interconnect the blocks in Simulink to arrange the appropriate model Test and run the interconnected model to finalize the debugging procedure for each part (block) Test and run the interconnected model to finalize the debugging procedure for each part (block)

9 9 Previous Approaches Lian,F.L. (University of Michigan, 2001) [14 ] Lian,F.L. (University of Michigan, 2001) [14 ] Nominated for best paper award Nominated for best paper award “ Performance Evaluation of Control Networks :Ethernet, ControlNet, “ Performance Evaluation of Control Networks :Ethernet, ControlNet, and DeviceNet ” and DeviceNet ” Wang, J. (Cornell University, 1999) [1] Wang, J. (Cornell University, 1999) [1] “ Efficient and Accurate Ethernet Simulation ” “ Efficient and Accurate Ethernet Simulation ” OPNET: can not easily combine with mechanical systems OPNET: can not easily combine with mechanical systems

10 10 How S - Function Simulation Works Initialization : - Initializes the SimStruct; a simulation structure that contains information about the S-function - Sets the number and dimensions of input and output ports - Sets the block sample time(s) Time Hit = (n * Period) + offset - Allocates storage areas and the sizes of arrays Simulation loop Start of simulation mdlinitializeSizes mdlinitializeSampleTimes mdlOutputs mdlTerminate mdlUpdate

11 11 Modelling of Ethernet Hardware Components Modelling of Ethernet Hardware Components Our modelling is based on : Event-driven simulation Event-driven simulation Transmission medium as a centralized active entity which: Transmission medium as a centralized active entity which: - Keeps track of packets sent by each station - Keeps track of packets sent by each station - Informs each station about the current state of the - Informs each station about the current state of the medium medium - Detects and computes the exact time a collision occurs - Detects and computes the exact time a collision occurs and sends out jam signals

12 12 Modelling of Ethernet: NIC NIC (Network Interface Card) NIC (Network Interface Card) - Performs those functions appropriate for the MAC - Performs those functions appropriate for the MAC (Media Access Control) layer protocol (Media Access Control) layer protocol - Generates frame - Generates frame NIC Media

13 13 Half Duplex versus Full Duplex Half Duplex : Only one device transmits at a time Half Duplex : Only one device transmits at a time (eg. Bus and Star topologies) (eg. Bus and Star topologies) Full Duplex: Transmit and receive simultaneously without listening across a dedicated link that is collision free Full Duplex: Transmit and receive simultaneously without listening across a dedicated link that is collision free Full duplex provides the benefit of increased bandwidth capacity and throughput Full duplex provides the benefit of increased bandwidth capacity and throughput

14 14 Sent frame > 64 bit CSMA/CD ( 1-PERSISTENT ) ready to send Listen Channel is idle Wait for T=IFG(Inter Frame Gap) 10 Mbps :9.6 μsec 100 Mbps :960 nsec 1000 Mbps :96 nsec Send Slot time=512 bit For multiple frames,wait for a period equal to the IFG between each frame Channel acquisition Transmission complete Collision counter clear Collision Sent frame > 512 bitSent frame < 512 bit Collision Counter++ Continue to transmit 32 bit collision enforcement Jam signal Wait for a random Period of time Completed Preamble of frame If collision counter<= 10,wait from 0 to 2^n-1 slot time If collision counter > 10,wait from 0 to 1024 (2^10 ) slot time If collision counter = 16,give up Back off Deferral Channel is busy Sent frame < 64 bit

15 15 Modelling of Ethernet: NIC (Cont.) SA DA Length IDVoltage Time Data In case of a Jam Signal: In case of a Jam Signal: DA = MAX_NODE_ETHERNET+1, DA = MAX_NODE_ETHERNET+1, Length = 32 bits, Length = 32 bits, ID = NULL, ID = NULL, V_JAM = V_XMIT + 1.0/(MAX_NODE_ETHERNET+1), V_JAM = V_XMIT + 1.0/(MAX_NODE_ETHERNET+1), where : where : V_XMIT is the transmission voltage. V_XMIT is the transmission voltage. Frame format in the proposed mechanical model

16 16 Modelling of Ethernet: NIC (Half-Duplex, Bus Topology) Idle Sending Receiving + Wait Back off End Wait for Jam End Back off Send Jam Wait for Back off Receiving Wait for Back off End And Jam End 7 12 9 4 3 465+8 7 4 9 7 6 49 4 3 Event 1: Data available to send. Event 2: End of transmission (No data available to send). Event 3: End of Jam Signal. Event 4: Receiving Jam signal. Event 5: Receiving data on the input port. Event 6: End of receiving data (By sensing the idle signal on the input port). Event 7: End of Back off. Event 8: No receiving buffer available, which causes the error signal. Event 9: Receiving data from another source in twisted pair cables or detect a collision by sensing higher voltage (U (4) >= V_CD) in the coaxial cables. NIC state diagram for the model of Bus topology with coaxial cable in half duplex mode

17 17 Modelling of Ethernet: NIC (Half-Duplex, Star Topology) Idle Sending Receiving + Wait Back off End Wait for Jam End Back off Send Jam Wait for Back off Receiving Wait for Back off End And Jam End 7 12 5 4 3 465+8 7 4 9* 7 5+8 6 49 4 3 NIC state diagram for the model of Star topology with twisted pair cable in half duplex mode

18 18 Modelling of Ethernet: NIC (Full-Duplex) Event 1: Data available to send Event 2: End of transmission (no data available to send) Event 3: Data available to send while we are receiving data on the input port Event 4: End of transmission and receiving data Event 5: Receiving data on the input port Event 6: End of receiving data (sensing the idle signal on the input port) Event 7 = Event 5 Event 8 = Event 6 Event 9 = Event 2 Event 10 = Event 1 (Note that in the code: event 7 stands for the no receiving buffer available and causes the error signal) Sending Receiving Idle 1 2 56 3 4 Sending + Receiving 78 910 NIC state diagram for the full duplex mode

19 19 Bus state diagram Modelling of Ethernet Hardware: Bus Bus Bus 10Base5 (Coaxial Cable) characteristics are the basis of modelling the propagation delay in medium 10Base5 (Coaxial Cable) characteristics are the basis of modelling the propagation delay in medium  4 i =1 V FIFOFIFO FIFOFIFO FIFOFIFO FIFOFIFO NIC2 BUS FABRIC NIC1NIC3NIC4 Carrier Collision Idle12 34 5 6 Event 1: One NIC transmit data Event 2: No transmission Event 3: More than one NIC transmit data Event 4: Event 1 Event 5: Event 2 Event 6: Event 3 A B C D

20 20 Modelling of Ethernet Hardware: Hub Hubs Hubs - Or multi port repeaters propagate signal through the networks and are used as network concentration points - Or multi port repeaters propagate signal through the networks and are used as network concentration points - A semi smart hub, which is not only a data distributor but also works as a collision detector and Jam generator is modeled in this study - A semi smart hub, which is not only a data distributor but also works as a collision detector and Jam generator is modeled in this study HUB A B C F G F E D G to D

21 21 Modelling of Ethernet Hardware: Hub (Cont.) Hubs : - Operate at physical layer of network - Amplify and generates signals; extend any runts (undersized frames, less than 96 bits) and reconstruct the preamble - Provide multiple connections or split the media - Detect the collision and send jam signal to all ports - Monitor the number of collisions and partition the port - Monitor the state of transceiver at each port Disadvantage : Can not filter network traffic Disadvantage : Can not filter network traffic

22 22 Modelling of Ethernet Hardware: Hub (Cont.) Hub state diagram Idle Event 1: One NIC transmit data Event 2: No transmission Event 3: More than one NIC transmit data Event 4: Transmission jam Event 5: End of Jam signal and one NIC start to transmit data Event 6: End of Jam signal Carrier Send Jam Collision Wait for Jam End1253 46

23 23 Modelling of Ethernet Hardware: Hub (Cont.) Simplified smart hub functionality diagram for regular operation A: BUFFER_SIZE_TRANSB: CABLE_DELAY C: START_P_DELAY_INPUT D: BUFFER_SIZE_REC F: START_P_DELAY_OUTPUTE: CABLE_DELAY HUB (Fabric) F D ECB A Port 1 Port 2 Port 3 Port 4 Port 2 Port 3 Port 4 Jam Signal Transmitter

24 24 Modelling of Ethernet Hardware: Hub (Cont.) Simplified smart hub functionality diagram in collision operation HUB (Fabric) Port 1 Port 2 Port 3 Port 4 Port 2 Port 3 Port 4 Jam Signal Transmitter

25 25 Modelling of Ethernet Hardware: Switch Switch Switch - Offers full duplex,dedicated bandwidth to segments or - Offers full duplex,dedicated bandwidth to segments or desktops.Do not forward collision signals from one segment desktops.Do not forward collision signals from one segment to another so: to another so: - Allows to build large,multi collision domain network - Allows to build large,multi collision domain network - Packet-based switches use one of three methods for routing - Packet-based switches use one of three methods for routing traffic: traffic: 1. Cut-through 1. Cut-through 2. Store-and-forward 2. Store-and-forward 3. Fragment-free 3. Fragment-free Note that, Many switches combine the two first methods. Note that, Many switches combine the two first methods. Switch A B C F G F E D G to D

26 26 Modelling of Ethernet Hardware: Switch There are three common types of buffer architecture: - There are three common types of buffer architecture: 1. Cross-bar switch 1. Cross-bar switch 2. Knockout switch 3. Shared media switch - Common buffer locations: - Common buffer locations: 1. Input Buffering (Disadvantage:HOL) 1. Input Buffering (Disadvantage:HOL) 2. Output Buffering 2. Output Buffering 3. Central Buffering 3. Central Buffering

27 27 2 3 4 3 4 1 1 2 4 1 2 3 Four-port switch with crossbar buffering architecture

28 28 Modelling of Ethernet Hardware: Switch Assumptions: - Full duplex switch with store and forward - Full duplex switch with store and forward - Each port will be connected to only one station and all - Each port will be connected to only one station and all the nodes send the same frame size the nodes send the same frame size - If one node have data for the same destination : - If one node have data for the same destination : priority mechanism to define which station should send priority mechanism to define which station should send first first Lower node index has the higher priority Lower node index has the higher priority

29 29 Testing and Verification Individually test, run and debug each subsystem model Individually test, run and debug each subsystem model Individually test, run and debug each S-function Individually test, run and debug each S-function Test and run the interconnected model to finalize the debugging procedure for each part (block) Test and run the interconnected model to finalize the debugging procedure for each part (block) Latency measurements Latency measurements

30 30 Simulation configuration used to test the NIC - Feeder : Traffic or packet generator - Feeder : Traffic or packet generator

31 31 Idle Sending Receiving + Wait Back off End Wait for Jam End Back off Send Jam Wait for Back off Receiving Wait for Back off End And Jam End 7 12 9 4 3 465+8 7 4 9 7 6 49 4 3 Illustration of paths followed in the simulation test

32 32 Feeder input used to test the NIC NIC output voltage and states

33 33 Simulation configuration used to test the BUS

34 34 feeder feeder1 feeder2 0200400600800100012001400160018002000 Time(BT) Comparison of feeder activity Output of Bus activity Simulation test for BUS

35 35 Simulation configuration used to test the Hub model

36 36 Voltage of inputs and output ports for the Hub

37 37 Simulation configuration used to test the Switch model

38 38 Comparison of inputs to switch ports

39 39 Comparison of outputs to switch ports

40 40 - Model 1: Half Duplex NIC with Coaxial Cable as Bus: - Model 1: Half Duplex NIC with Coaxial Cable as Bus: Interconnection of four NICs in half duplex mode with 10Base5 (Coaxial cable) Bus

41 41 Signal activity on the BUS

42 42 Model 2: Half Duplex NIC, Twisted Pair Cable and 4 Ports Hub : - Model 2: Half Duplex NIC, Twisted Pair Cable and 4 Ports Hub : Interconnection of four NIC in half duplex mode

43 43 Illustration of voltages on the input / output ports of Hub model

44 44 Model 3: Full Duplex NIC, Twisted Pair Cable and 8 Ports Switch: - Model 3: Full Duplex NIC, Twisted Pair Cable and 8 Ports Switch: Interconnection of four NICs in half duplex mode with 10BaseT(Twisted pair) as media and eight-port switch

45 45 Voltages on the input / output ports of the Switch model

46 46 Latency Measurements : Switch Time T dclock T dtx_NIC T drx_NIC T dround T1 T1 T2 T2 T dtx_p T drx_p T switch Latency definitions for the Switch test 3COM 3C16477 Baseline Gigabit Switch time delay test

47 47 Testing and Verification (Cont.) Validating the accuracy by comparing the performance measurements results Validating the accuracy by comparing the performance measurements results Note that: Note that: - All the simulation tests have used a zero releasing policy - All the simulation tests have used a zero releasing policy - Limited number of messages to lower the traffic loads on the network medium and for the stability reason and to escape from the intensive channel capture issue - Limited number of messages to lower the traffic loads on the network medium and for the stability reason and to escape from the intensive channel capture issue

48 48 Test 1: Variation in number of nodes Average time delay versus number of network nodes Network utilization/efficiency versus number of network nodes

49 49 Test 2: Variation in number of transmitted messages Average time delay versus number of messages per node to transmit Network utilization / efficiency versus number of messages per node

50 50 Test 3: Variation in frame size: Average time delay versus frame size comparison for 2 and 4 node in networks

51 51 Application to Distributed Simulation Simulating networked mechanical models : Simulating networked mechanical models : X1 b1 M1M2 K1K2K3 b2b3 X2 Mass spring system

52 52 Application to Distributed Simulation V 2 X 2 V 1 X 1 Y= 1 1 1 1 0 0 00 00 00 0 000 b 2 / M 1. V2V2. V1V1 V1V1 V2V2 - (K 3 + K 2 ) / M 2 - (b 2 + b 3 ) / M 2 = K 2 / M 2 - (K 1 + K 2 ) / M 1 01 - (b 1 + b 2 ) / M 1 V 2 X 2 V 1 X 1 00 00 b 3 / M 2 K 2 / M 1 01 A1A1 A2A2 B1B1 B2B2 State space of dynamic equation of motion Z 2 (k + 1) = A 2d Z 2 (k) + B 2d Z 1 (k) Z 1 (k + 1) = A 1d Z 1 (k) + B 1d Z 2 (k) Where: A 1d = I + A 1  t A 2d = I + A 2  t B 1d = B 1  t B 2d = B 2  t

53 53 Simulation using one processor Simulation configuration of mass-spring system, simulation on one computer Simulation of mass-spring model

54 54 Distributed mass spring model X2V2X2V2 X1V1X1V1 X2V2X2V2 X1V1X1V1 NODE 1 NIC1 NODE 2 NIC2 Switch 13245678 Schematic connection of nodes and switch in the model

55 55 Distributed mass spring model using full duplex Ethernet protocol

56 56 Comparison of the signals in one processor simulation model and distributed simulation after switch

57 57 Conclusions Main results and contributions:  A new modular / scalable simulation package for Ethernet for most hardware components  Simulation of network time delays  A new combined discrete network / continuous mechanical system simulation framework  Testing and verification

58 58 Future Work  Implement Gigabit Ethernet simulation.  Improve switch model :half duplex mode, learning ability and spam algorithm.  Application to design and analysis of real-time Ethernet based distributed simulation and control  Modelling of other Ethernet hardware such as bridges and routers

59 59 Thanks

60 60 Ethernet Frame IEEE 802.3 32 16 48 8 S Length Preamble F DA SA or Data/LLC FCS D Type S Length Preamble F DA SA or Data/LLC FCS D Type 56 48 46 to 1500 I/G U/L LLC Data Pad Start Frame Delimiter (SFD): Bit sequence, indicates the actual start of the frame and enables the receiver to distinguish the first bit from the rest of the frame. I/G: Individual physical / Group address. U/L: Universal / Local address. LLC header: Logical link control header. Frame check sequence (FCS): A 32bit Cyclic Redundancy Check (CRC).

61 61 Latency Measurement: Hub / Switch Parallel Port Cable Node1 NIC Hub/Switch Node2 NIC

62 62 Network efficiency delay versus frame size comparison for 2 and 4 node networks Network utilization versus frame size comparison for 2 and 4 node networks Test 3: Variation in frame size:

63 63 Example of real-time distributed system CAE marine simulator CAE marine simulator


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