1. www.vlsi.itu.edu.tr23.10.2015 1 Very Large Scale Integration II - VLSI II Memory Structures Hayri Uğur UYANIK Devrim Yılmaz AKSIN ITU VLSI Laboratories Istanbul Technical University

2. www.vlsi.itu.edu.tr23.10.2015 2 Outline History Lesson General Memory Structure Memory Cell Types – Volatile SRAM DRAM – Non-Volatile MPROM EPROM OTP & UV-EPROM E 2 PROM FeRAM Memristor Sense Amplifiers – Voltage Sense Amplifiers – Current Sense Amplifiers Address Decoder Memory Modelling In Verilog References

3. www.vlsi.itu.edu.tr23.10.2015 3 History Lesson Delay line memory – Piezoelectric pulses within mercury – One of the earliest electronic (?) memory – 1000 word storage

4. www.vlsi.itu.edu.tr23.10.2015 4 General Memory Structure

5. www.vlsi.itu.edu.tr23.10.2015 5 Memory Cell Types Volatile – SRAM – DRAM Non-Volatile – MPROM – EPROM OTP UV-EPROM E 2 PROM – FeRAM – Memristor

6. www.vlsi.itu.edu.tr23.10.2015 6 SRAM Static Random Access Memory

7. www.vlsi.itu.edu.tr23.10.2015 7 SRAM Not area efficient  No special semiconductor process Fast Low power consumption Easy to communicate Used in – Embedded systems – CPU Cache – FPGA CPLD LUT

8. www.vlsi.itu.edu.tr23.10.2015 8 DRAM Dynamic Random Access Memory

9. www.vlsi.itu.edu.tr23.10.2015 9 DRAM Area efficient Very area efficient Needs special semiconductor process  Slow  Hard to communicate with  High power consumption  Needs refreshing  Used in – Computer primary storage – Video card primary storage – Cell Phones, PDAs

10. www.vlsi.itu.edu.tr23.10.2015 10 DRAM Types Asynchronous DRAM Synchronous DRAM (SDRAM) – Single Data Rate (SDR SDRAM) – Dual Data Rate (DDR SDRAM) Both rising and falling edge Memory cells are slow compared to bandwidth demand Bandwidth is increased by increasing the I/O buffer data rate (DDR2 and DDR3) – Dual DDR Communicate with two different RAM slots at the same time

11. www.vlsi.itu.edu.tr23.10.2015 11 DRAM Types

12. www.vlsi.itu.edu.tr23.10.2015 12 Dual Ported RAM SRAMs and DRAMs can be dual ported – can read from and write to two different addresses at the same time – Mostly effective in Video processing – One port filling the RAM, one port is reading for display CPU registers FIFOs

13. www.vlsi.itu.edu.tr23.10.2015 13 MPROM Mask Programmable ROM

14. www.vlsi.itu.edu.tr23.10.2015 14 MPROM Programmed at the fab  – Route metal interconnects – Increase V T Change channel implant Change gate oxide thickness One time programmable  Only few masks are changed Cheap in large volume Used in – Old video games – Sound data in electronic music instruments – Electronic dictionaries

15. www.vlsi.itu.edu.tr23.10.2015 15 OTP & UV-EPROM One Time Programmable ROM UV Erasable Programmable ROM

16. www.vlsi.itu.edu.tr23.10.2015 16 OTP & UV-EPROM 1. High V G and V D creates hot electrons 2. They penetrate gate oxide 3. They become trapped in the floating polysilicon 4. Additional negative charge below the gate increases V T (For a 5V ROM, V T increases from 1V to 8V)

17. www.vlsi.itu.edu.tr23.10.2015 17 OTP & UV-EPROM OTP and UV-EPROM are the same – OTP has a opaque plastic package (cheaper) – UV-EPROM has a package with transparent quartz window (expensive)  Need special semiconductor process  Slow write  High power consumption when writing  Fast read OTP data is permanent  UV-EPROMs can be erased – When exposed to UV light for 20 minutes 

18. www.vlsi.itu.edu.tr23.10.2015 18 E 2 PROM Electrically Erasable Programmable ROM

19. www.vlsi.itu.edu.tr23.10.2015 19 E 2 PROM Erasing: – V D =0, V S =0, V G =High (e.g. 15V) – Floating gate becomes positively charged Fowler-Nordheim Tunneling – V T below floating gate (V TFG ) drops Making Open Circuit: – EPROM like operation – V D =0, V S =High (e.g. 12V) V G =V TCG – Channel present under control gate – Hot electrons penetrate gate oxide – V TFG increases

20. www.vlsi.itu.edu.tr23.10.2015 20 E 2 PROM Fast read/write Need special semiconductor process  Low power consumption when writing

21. www.vlsi.itu.edu.tr23.10.2015 21 FeRAM Ferroelectric RAM

22. www.vlsi.itu.edu.tr23.10.2015 22 FeRAM Fast read/write Need special semiconductor process  Low power consumption Destructive reading 

23. www.vlsi.itu.edu.tr Memristor Missing circuit element for 37 years – Concept: Leon Chua - 1971 – First Realization: HP Labs - 2008 Final addition to RLC team 23.10.2015 23

24. www.vlsi.itu.edu.tr Memristor Charge dependent resistance (memristance) Applied voltage or current changes charge (thus the resistance) – Resistance is stored in a non-volatile manner – Can be used to store digital data – Must be read with an AC signal for non-destructive reading (AC does not change stored charge) 23.10.2015 24

25. www.vlsi.itu.edu.tr Memristor Best of both worlds – Non-volatile – Fast (~f DRAM /10) – Dense (~1Pb/cm 3 ) Has a potential to alter the computer programming paradigm – No need for two sets of memories (fast & volatile for computing, slow & non-volatile for data storage) 23.10.2015 25

26. www.vlsi.itu.edu.tr23.10.2015 26 Sense Amplifiers Voltage Sense Amplifiers

27. www.vlsi.itu.edu.tr23.10.2015 27 Sense Amplifiers Current Sense Amplifiers

28. www.vlsi.itu.edu.tr23.10.2015 28 Address Decoder module ADD_3_8 (in, out); input [2:0] in; output [7:0] out; reg [7:0] out; always @(in) begin case (in) 3'b000 : out = 8'b00000001; 3'b001 : out = 8'b00000010; 3'b010 : out = 8'b00000100; 3'b011 : out = 8'b00001000; 3'b100 : out = 8'b00010000; 3'b101 : out = 8'b00100000; 3'b110 : out = 8'b01000000; 3'b111 : out = 8'b10000000; endcase end endmodule

29. www.vlsi.itu.edu.tr23.10.2015 29 Memory Modelling In Verilog parameter RAM_WIDTH = ; parameter RAM_ADDR_BITS = ; reg [RAM_WIDTH-1:0] [(2**RAM_ADDR_BITS)-1:0]; reg [RAM_WIDTH-1:0] ; [RAM_ADDR_BITS-1:0] ; [RAM_WIDTH-1:0] ; initial $readmemh(" ",,, ); always @(posedge ) begin if ( ) [ ] ; else [ ]; end

30. www.vlsi.itu.edu.tr23.10.2015 30 References http://www.ieee.org/portal/cms_docs_sscs/sscs/08Winter/sunami- fig3.jpg http://en.wikipedia.org http://www.seas.upenn.edu/~ese570/1244.pdf http://www.xtremesystems.org/forums/showthread.php?208829- Memory-101-SDR-vs-DDR1-vs-DDR2-vs-DDR3 http://www.xtremesystems.org/forums/showthread.php?208829- Memory-101-SDR-vs-DDR1-vs-DDR2-vs-DDR3 http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC09.PDF http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC07.PDF http://spectrum.ieee.org/semiconductors/design/the-mysterious- memristor http://spectrum.ieee.org/semiconductors/design/the-mysterious- memristor http://www.eecg.toronto.edu/~kphang/papers/2001/igor_sense.pdf Xilinx Documentation