1. Encoders and Decoders

2. Encoding Suppose we have 8 input signals and only one amongst them is active at any point in time. – Clearly we can have 8 bits to represent this and have only 1 bit set. – But this would necessitate 8 wires going all the way to the part of the circuit using this information. Can we be more efficient in the number of bits? And therefore save on the wiring? Binary logic allows us to use just 3 bits to signal which of the 8 input lines were active. – Log 2 8 = 3

3. 8 to 3 encoder TT Priority is given to the most significant bit that is high.

4. Encoder Logic

5. Decoding Complimentary to encoding Select one of k output lines to be high based on the ln k bit input. Fun challenge: Can you design a full adder using a decoder?

6. Full Adder with a Decoder A (Add end) B (Aug end) CinSumCarry Out 00000 01010 10010 11001 00110 01101 10101 11111 F s = Σ m (1,2,4,7) F co = Σ m (3,5,6,7) 3 to 8 Decoder Enable signal – If its 1, it cuts off power to the IC – electrically disconnect without unplugging

7. Multiplexers (MUX) Motivation – cost/function is not linear – => 100 gates does not cost 10 times as much as 10 gates (in fact, far less – perhaps 1.1). – This motivates us to build larger circuits on a single chip rather than raw gates on it (pin issues). – Often called MSI/LSI/VLSI. Encoders/Decoders are examples So is a multiplexer

8. MUX Switches in one of the inputs to the output based on selector inputs. 4 to 1 Mux i0 i1 i2 i3 s0s1 F = S1’S0’i0 + S1’S0 i1 + S1 S0’i2 + S1 S0 i3 Application? Telephony!

9. FA with Mux? 01 10 01 10 Ci AB 00 01 11 10 0 1 K Map for Sum (S) 00 01 11 01 AB 00 01 11 10 0 1 K Map for Cout When AB=00, the SUM is just Ci, so connect Ci to i0. Similarly … Connect i1 to Ci’ Connect i2 to Ci’ Connect i3 to Ci When AB=00, the Cout always 0. Connect i1 to Ci Connect i2 to Ci Connect i3 to 1 AB becomes our control signal to the Mux

10. FA With Mux A B Cin 0

11. Challenge The chief challenge is to match the requirements to the capabilities of the devices that are out there. – Most muxes come as 2 Muxes to an IC from which we can make a full adder. Almost ANYTHING with a 3 or 4 variable K Map can be done with either a 4 to 1 or 8 to 1 Mux.

12. Programmable Logic Arrays

13. Multi Purpose Imagine a circuit which could realize any truth table you want and perhaps even different truth tables at different times! Similar to microprocessors, PLAs are “reconfigurable” – Not as flexible as microprocessors – Programmability on a smaller, less complex scale. Another approach to constructing logic – Different from gate level design PROMs, EPROMs etc. are examples of PLAs.

14. Approach Think of a TT as a hashmap The key is the input The contents of the memory location indexed by the key is the output 000…. 001… 0101000 0111100 100… 101… 1101101 1111100 Inputs Outputs So, what is reconfigurable about this? The ability to change the contents of the cells on the RHS of the TT

15. Persistence? Wont the contents of this memory get erased when the device is powered off? UVEPROM, Flash - examples of persistent memory. Electronically alterable or with UV Radiation.

16. Now for the logic 3 Inputs – X0 to X2 Realizing Minterms with AND array

17. The TT we want x2x1x0z1z0 00000 00110 01000 01110 10011 10100 11000 11101 Wiring the AND array for the 4 Minterms we want Minterms: x0 x1’ x2’ x0 x1 x2’ x0’ x1’ x2 x0 x1 x2

18. Now for the outputs Z0 = Σ m(4, 7) Z1 = Σ m(1, 3, 4) OR Array for the outputs

19. “Programming a PLA” What does it mean to program a PLA? See the black dots? Those are connections made between wires. In effect "programming" the wires means to make the connections within the PLA. Configurable might be a better word than programmable, but that's the name that stuck.

20. Size of a PLA? Given n variables, it would seem necessary to have 2 n vertical wires (for the AND gates), one for each possible minterm. However, this grows VERY quickly. So, sometimes there aren't 2 n vertical wires. m OR gates for m outputs

21. Sequential Logic

22. Two kinds of logic Combinational logic – implement boolean expressions Sequential Logic – Adds an element of “feedback” – The outputs not only depend on the present inputs but on past behavior. – Needed for many situations – traffic controller We need to remember the state we are in before we transition to another state. If the light is green and 90 seconds have passed, change the light to Yellow.

23. Combinational Logic ++ Combinational Logic Block Memory Feedback Loop

24. Latches and Flip Flops, Clocks

25. Basic Building Blocks of Memory - Latches A Basic NOR Latch Incorporates feedback – what does it do? Start with S = 1 and R = 0 Then Q’ = 0 and Q = 1 Now make S = 0 and R = 0 then Q’ remains 0 and Q remains 1 Now make S = 0 and R = 1 then Q becomes 0 and Q’ will become 1 Again make S = 0 and R = 0 (with Q = 0 and Q’ = 1) then Q remains 0 and Q’ remains 1 (contrast this with case 2 above)

26. Case 2 and 4 have identical inputs but have different outputs because of the memory derived from case 1 and 3 respectively. What happens if I make both S and R be 1? – Q and Q’ are both 0 which makes no sense. If I now make S= 0 and R= 0 I can get either: – Q = 0, Q’ = 1 – Q = 1, Q’ = 0 – Depending on which gate you analyze first or “fires” first. Hence the output of the latch when S = R = 0 AFTER S = R = 1 is unreliable and should not be used.

27. TT of the SR Latch SRQQ’ 00Memory State (As before) 0101 1010 11Not Used state Regardless of previous State S is the setting input R is the Resetting input

28. S-R Latch with Nand Note the inputs are complements of the inputs for the NOR latch What if we did not have the complemented inputs? The TT changes accordingly: 0,0 will be the “not used” state and 1,1 will be the memory state

29. Issues with the design The “not used” state is confusing. Why should I give two inputs to store 1 bit??? When the input changes (because of whatever reason) the outputs can change even though I may not want the change. – Variations in input signals. – I don’t really have control over the persistence of memory. Latches are therefore only the building blocks of memory

30. Clocked Latches or Flip Flops Incorporates a control mechanism to ensure that only when the control is high are any latch inputs accepted.

31. Why are clocks really useful? It allows us to synchronize multiple parts of a circuit and smooth out the difference in performance of various stages. It allows us to sequence a set of operations.

32. The latch’s state can be changed only when the clock is high. But remember there are gate delays! The trick is to have the inputs be ready just before the clock goes high so that the inputs are applied when the clock goes high and then you have the entire high part of the cycle as the delay tolerance of the circuit. What should be the frequency or clock period of the clock? – The smallest period is decided by how long the latch needs to process the input.

33. Avoiding the 1-1 input state S-R Flip Flop D Clock Q Q’ D (for Data) Flip flop – the simplest 1 bit storage element

34. Can we use the wasted (not used) state? We have added a stage of gates to the SR Flip Flop What happens when: Clk=1, J=K=1? Assume initially: Q=1, Q’=0 Output changes to 0,1 from 1,0 How about when: Q=0, Q’=1 Output changes to 1,0 from 0,1 So, when Clk=1, and J=K=1 the output races between 0 and 1 with a frequency that depends on the gating speed. Now if only we could control this race!

35. Master Slave JK Flip Flop Two Flip flops with: a)Complementary clocks and b)one feedback from output of the second stage to input of the first stage What does this do?

36. A Toggling Flip Flop What happens if we take a JK flip flop and tie the two inputs together? When the CLK = 0, its in Memory State and the input does not affect it When the CLK = 1 and T = 0 its ALSO a Memory State. When the CLK = 1 and T = 1, it will be in Toggle state, toggling once every (rising edge or falling edge of the) clock cycle.

37. Registers

38. Memory A latch is a simple 1 bit storage element. We can string a set of D latches together to make a higher order storage element. The issue: To keep the data for a while, I must turn the clock off after storing the data But the clock in the computer is common and is of a much higher frequency than what persistent storage needs

39. Persistence Behavior We need an independent control to keep the data around. Desired behavior: Set when the data is available and then store in it. Needs an additional control input – Write Enable or Load

40. Clearing a register Similar to controlling when data gets loaded, we can also control when data gets cleared so that junk is not read unintentionally off the register. Think about how to do this…

41. Shift Registers In the registers we have seen so far, inputs and outputs are fed in and read in parallel There may be situations involving serial I/O devices that need a serial stream of bits to be stored and then read in parallel (and vice versa)

42. Modes of Operation Serial O/PParallel O/P Serial I/PSISOSIPO Parallel I/PPISOPIPO Load and clear controls still exist as before. Registers which offer all modes are called Universal Shift Registers

43. State Machines

44. What are SMs? A set of states A set of transitions triggered by events

45. A more complex example – the TCP Protocol State Machine

46. Many examples Traffic light controller Elevator controller Airplane takeoff controller etc. etc. In each state, the SM can produce an output. We can also think of a SM as a clocked sequential circuit. – A 2 bit counter – has 4 states (00, 01, 10, 11) and cycles through these states with a clock pulse.

47. Representing a SM Input X CLK to trigger the transition Output Z Current State (2 bits) Memory (D FFs)

48. Counter as a state machine A counter cycles through a sequence – usually contiguous. However, lets do something different Our counter: – 6 states – S0 – S5 – Sequence: [1,4,3,5,2,6] cycling back to 1 after 6. – How many state variables? 3 for 6 states.

49. State s ABC S0001 S1100 S2011 S3101 S4010 S5110 S2 S0 S1 S3 S4 S5 3 State Variables (A, B, C) No external Inputs in this case

50. CLK to trigger the transition Current State & Output (3 bits) D0 D1 D2 Q0 Q1 Q2 Counter Combinational logic A, B, C A+, B+, C+

51. How about the combinational logic? ABCA+A+ B+B+ C+C+ 000XXX 001100 010110 011101 100011 101010 110001 111XXX X0 10 1X 10 A 00 01 11 10 0 1 K Map for A+ BC A+ = A’Similarly B+ = AB’ + A’C’ andC+ = AC’ + BCA+ = A’Similarly B+ = AB’ + A’C’ andC+ = AC’ + BC