1. Robust Low Power VLSI R obust L ow P ower VLSI A Charge Pump Based Receiver Circuit to Reduce Interconnect Power Dissipation Aatmesh Shrivastava

2. Robust Low Power VLSI 2 Processor Power Power of CPU has been increasing with CMOS scaling. Reduced battery life and reliability issues due to heating. Design techniques needed to stop this trend. Source Intel

3. Robust Low Power VLSI 3 Power Components in a chip Leakage Power= VDD* I L, Dominates when idle. Switching Energy= C*VDD 2, Dominates when active. In this talk we focus on reducing switching energy. ILIL C

4. Robust Low Power VLSI 4 Interconnect Energy Energy= α(C T +C W )V DD 2 C T is device cap & C W is the wire cap Traditionally C T >> C W With scaling device became smaller and C T ~C W Significant energy is wasted in parasitic wires.

5. Robust Low Power VLSI 5 Interconnect Power Magen et. al. Interconnect accounts for >50% of power in a modern microprocessor [2]. In this paper we present circuit technique to reduce this power/energy.

6. Robust Low Power VLSI Outline  Reducing Interconnect energy through voltage scaling.  Driver Design  Receiver  Literature Review  Proposed Interconnect Receiver  Charge Pump  Proposed Circuit  Results  Energy Savings in a Processor 6

7. Robust Low Power VLSI 7 Voltage Scaling for interconnects Interconnects run at VDDI, Energy= α(C T *V DD 2 +C W *V DDI 2 ) VDDI< VDD will save energy. Driver converts VDD level signal to VDDI while receiver converts VDDI to VDD signal Logic runs at rated VDD, wires at reduced VDDI Key tradeoff :- Performance overhead vs Power.

8. Robust Low Power VLSI 8 Driver Asymmetric source follower driver [4] Two NMOS transistors are used at output stage A signal at logic level ( 1V) is converted to a signal interconnect level (0.3V) We use this driver in our proposed interconnect circuit. 1 ON OFF ON OFF 0

9. Robust Low Power VLSI 9 Single Ended Receiver Receiver Design plays an important role in power performance trade-off. Receiver converts the signal at interconnect level back to the logic level Poor performance, VDDI > 2*V T. VDDI ON 0 OFF ON

10. Robust Low Power VLSI 10 PPA : Power Performance Prior Art In prior art either energy saving is less or performance is poor. SchemesB/W (Ghz) Swing (V) Normalized Energy Basic ( no scaling)>111 Single-ended [4,5,7]<0.250.6 Differential [8-10]>10.050.8 Capacitive [6]<0.250.050.2

11. Robust Low Power VLSI 11 Delay vs Energy/bit : Prior Art Existing solutions do not address power and performance in conjunction.

12. Robust Low Power VLSI 12 Proposed receiver ckt Charge-pump is used. It boosts the signal to three times the interconnect swing Good performance and much lower power

13. Robust Low Power VLSI 13 Charge Pump : Working principle Two buckets with water at height h. Water level in bucket rises Q Q Two caps with Charge Q Q=CV If the charge of one cap is dumped on another 2Q 2Q=CV1, so V1=2Q/C=2*V Charge pump is a circuit that does this charge transfer.

14. Robust Low Power VLSI 14 Charge Pump : To increase swing Switches φ1 and φ2 close at non-overlapping time When φ1 closes, 1 gets charged to VDDI, When φ2 2 gets charged to VDDI and so 1 goes to VDDI Circuit boosts the signal 2 times here. 1 2 2 1

15. Robust Low Power VLSI 15 Proposed receiver ckt Charge-pump is used. It boosts the signal to three times the interconnect swing Good performance and much lower power

16. Robust Low Power VLSI 16 Simulation results Reduced swing interconnect signal gets reconstructed with good performance. INOUT

17. Robust Low Power VLSI 17 Delay vs Energy/bit Proposed Solution gives very good performance and very low energy.

18. Robust Low Power VLSI 18 Energy savings in a processor 4-core Alpha processor was simulated using m5 simulator Data bus b/w L1-L2 cache is long, power consuming interconnect. Long Interconnect

19. Robust Low Power VLSI 19 Energy savings in a processor Data-Bus of alpha was implemented using differential, basic and proposed interconnect circuit. Over the set of splash benchmarks, the proposed interconnect saves up to 70% of energy.

20. Robust Low Power VLSI 20 PPA : Power Performance Area Novel interconnect circuit has very good PPA metric SchemesB/W (GHz) Swing (V) Norm. EnergyArea of 1 repeater Basic>1112X Single Ended [4,5,7] <0.250.6 15-24X Differential [8-10] >10.050.8100-250X Capacitive [6]<0.250.050.2NA This Work>10.3 22X

21. Robust Low Power VLSI 21 Thank You

22. Robust Low Power VLSI References 1.P. Kogge, K. Bergman, S Borka, et. al, “ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems” DARPA/IPTO, September 2008 2.D. Liu and C. Svensson, “Power Consumption Estimation in CMOS VLSI chips” IEEE Journal of Solid-State Circuits, Vol-29 No-6, June 1994. 3.E. Kusse and J.M. Rabaey, “Low-Energy Embedded FPGA Structures” IEEE International Symposium on Low Power Electronics Design, August 1998. 4.H. Zhang, V. George and J.M. Rabaey, “Low-Swing On-Chip Signalling Techniques: Effectiveness and Robustness” IEEE Transactions on Very Large Scale Integration (VLSI), Vol-8 No-3, June 2000 5.J.C.G. Montesdeoca, J.A. Montiel-Nelson and S. Nooshabadi, “CMOS Driver Receiver Pair for Low Swing Signalling for Low Energy On-chip Interconnects” IEEE Transactions on Very Large Scale Integration (VLSI), Vol-17 No-2, February 2009. 6.R. Ho, I. Ono, F. Liu, A. Chow, J. Schauar and R. Drost, “High Speed and Low Energy capacitively driven wires” IEEE International Solid State Circuits Conference, February 2007. 7.M. Ferretti and P.A. Beere “Low Swing Signaling Using a Dynamic Diode-Connected Driver” European Solid-State Circuits Conference, September 2001. 8.A. Narshimha, M. Kasotiya and R. Sridhar “A Low-Swing Differential signaling Scheme for on-chip Global Interconnects” International Conference on VLSI Design, January 2005. 9.N. Tzartzanis, W.W. Walker “Differential Current Mode Sensing for Efficient On-Chip global Signaling” IEEE Journal of Solid State Circuits, Vol-40 No-11, November 2005. 10.H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada and K. Masu, “A Bidirectional and Multidrop Transmission Line Interconnect for Multipoint to Multipoint On-Chip Communication” IEEE Journal of Solid State Circuits, Vol-43 No-4, April 2008. 11.V. Alder and E.G. Friedman, “Repeater Design to Reduce Delay and Power in Resistive Interconnects”. IEEE Transactions on Circuits and Systems-II, Vol-45 No-45, May 1998. 12.P.E. Allen and D.R. Holberg., “CMOS Analog circuit design” Oxford Press 2002. 13.R.E. Kessler, E.J. McLellan and D.A. Webb, “The Alpha 21264 Microprocessor Architecture” International Conference on Computer Design, October 1998. 14.N.L. Binkert, R.G. Dreslinski, L.R. Hsu, K.T. Lim, A.G. Saidi and S.K. Reinhardt, “The M5 Simulator: Modeling Networked Systems” IEEE Micro, July 2006. 22

23. Robust Low Power VLSI 23 Back Up

24. Robust Low Power VLSI 24 More Plots

25. Robust Low Power VLSI 25 Charge Pump

26. Robust Low Power VLSI 26 Pulse Generator

27. Robust Low Power VLSI 27 Proposed Circuit

28. Robust Low Power VLSI 28 Timing diagram

29. Robust Low Power VLSI 29 Differential Receiver Output can swing from VDD to VDD-IR. If I/R is large signal can reach full swing. It also converts low swing to high swing Good Performance. Two wires/bit and static current :Power Overhead. Strong Weak