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1 Gerhard Lutz MPI-Semiconductor Laboratory, München Vertex2003 Lake Windermere, Sept.16, 2003 DEPFET development at the MPI Semiconductor Laboratory.

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Presentation on theme: "1 Gerhard Lutz MPI-Semiconductor Laboratory, München Vertex2003 Lake Windermere, Sept.16, 2003 DEPFET development at the MPI Semiconductor Laboratory."— Presentation transcript:

1 1 Gerhard Lutz MPI-Semiconductor Laboratory, München Vertex2003 Lake Windermere, Sept.16, 2003 DEPFET development at the MPI Semiconductor Laboratory

2 G.Lutz, RAL Sept.12, 20032 Content Introduction DEPFET detector-amplifier structure Principle and properties Applications DEFETs as pixel detector In x-ray astronomy (XEUS) In particle colliders (TESLA) DEPFET production in Munich Vertex detector for TESLA Detector thinning technology Readout electronics Summary and conclusions

3 G.Lutz, RAL Sept.12, 20033 Introduction DEPFET detector development at Munich is part of our activities in connection with instute experiments Own laboratory is supported by two Max-Planck Institutes Active in particle physics and astrophysics (X-ray astronomy) Complete semiconductor processing line in house Detectors mostly based on own concepts Present major project: DEPFET pixel detectors

4 G.Lutz, RAL Sept.12, 20034 The Depleted Field Effect Transistor (DEPFET) Kemmer+Lutz 1985 Device concept: Combination of FET transistor with Sideward depletion (Drift chamber) Gatti + Rehak 1984

5 G.Lutz, RAL Sept.12, 20035 DEPFET properties Field effect transistor on top of fully depleted bulk All charge generated in fully depleted bulk assembles underneath the transistor channel steers the transistor current Combined function of sensor and amplifier low capacitance and low noise Signal charge remains undisturbed by readout repeated readout Complete clearing of signal charge no reset noise Full sensitivity over whole bulk Thin radiation entrance window on backside DEPFET structure and device symbol

6 G.Lutz, RAL Sept.12, 20036 Operation modes of DEPFET DEPFET operation properties Charge collected and stored in internal gate both in transistor on mode and also in transistor off mode Charge is not destroyed by measuring it DEPFET operation modes: 1)Normally on (continuous operation, occasional reset) real time operation 2)Normally off (charge collection in powerless condition) integration mode operation

7 G.Lutz, RAL Sept.12, 20037 Simulations operation modes Real time mode: Signal collection with DEPFET on Real time signal processing (shaping) Clear internal gate from time to time Drain current Charge in internal gate Applications: Readout element of drift detectors or CCDs

8 G.Lutz, RAL Sept.12, 20038 Simulations operation modes Integration and Sample mode: Signal collection with turned off DEPFET Turn on DEPFET by gate First current measurement Clear internal gate Remeasure current and take difference Drain current Charge in internal gate Applications: Building block of pixel detectors Readout element of drift detectors

9 G.Lutz, RAL Sept.12, 20039 DEPFET types: MOS-depletion MOS-enhancement JFET Open (rectangular) geometry Closed (circular) geometry DEFET applications Readout element of Drift detector CCD Element of pixel detector

10 G.Lutz, RAL Sept.12, 200310 DEPFET 55 Fe Spectrum Single DEPFET (JFET, closed geometry) At room temperature Cooled

11 G.Lutz, RAL Sept.12, 200311 MPI experiments needing DEPFETs X-ray astronomy: XEUS (next generationEuropean X-ray observatory) successor of XMM-Newton Particle physics: TESLA vertex detector Both experiments need pixel detectors

12 G.Lutz, RAL Sept.12, 200312 DEPFET pixel matrix - Read filled cells of a row - Clear the internal gates of the row -Read empty cells Difference of readings (filled/empty) mesures charge Low power consumption Fast random access to specific array regions

13 G.Lutz, RAL Sept.12, 200313 Prototype DEPFET-System developed with Bonn University 64 x 64 matrix with 50 x 50 µm 2 pixel designed for Biomedical Applications clock rate : 50 kHz achieved noise in matrix: ~50e 64x64 pixel DEPFET-Matrix JFET type Closed geometry (50x50µm 2 pixel) low noise Readout-Chip: CARLOS Control-Chip: Switcher

14 G.Lutz, RAL Sept.12, 200314 results with prototype system Single-pixel spectra: ENC = 4.8 +/- 0.1 e - 55 Fe-spectra @ 300K spatial resolution: ~ 9µm (with 50x50 µm 2 pixel) ~ 3.2 mm Matrix-picture with 55 Fe: [J.Ulrici, Bonn] Autoradiography with 3 H: ~ 10 mm detection of Tritium 3 H (5,6keV mean energy)

15 15 MPI semiconductor laboratory... with modern, custom made facilities...... for a full 6 silicon process line800 m ² cleanroom up to class 1... mounting & bonding test & qualificationsimulation, layout & data analysis

16 G.Lutz, RAL Sept.12, 200316 Future X-ray Mission: XEUS (X-ray Evolving Universe Spectroscopy) Experiment Increase in collecting area (factor 100) Increase of collection area (0.5 to 6- 30m 2 ) Increase in focal length (7.5 to 50m) Optics and focal imaging on separate satellites Focal detector requirements: faster readout (factor 10 to 100) avoidance of ''out of time'' events larger size focal detector (7x7cm 2 ) smaller pixel size (5050μm 2 ) Detector requirements can be met with DEPFET pixel detectors Scientific aim: investigation of the universe at an early evolution stage: - early black holes - evolution and clustering of galaxies - evolution of element synthesis 6% out of time events in XMM

17 G.Lutz, RAL Sept.12, 200317 Present DEPFET pixel detector development for XEUS and TESLA LayerModule sizeNo. Of modules I13 x 100 mm1 x 8 II22 x 125 mm2 x 8 III22 x 125 mm2 x 12 IV22 x 125 mm2 x 16 V22 x 125 mm2 x 20 Total 500 MPixel (with 25x25 µm Pixelsize) (read out speed 50 MHz) Options: CCD MAPS HAPS DEPFET TESLA vertex detector Thin Fast Low power In collaboration with Bonn (N.Wermes) and Mannheim (P.Fischer)

18 G.Lutz, RAL Sept.12, 200318 Design of DEPFET pixel detectors Type of DEPFETS: MOS-depletion type XEUS: zylindrical geometry TESLA: rectangular geometry Technology: 6 Inch Double-poly, double metal, Self-aligned

19 G.Lutz, RAL Sept.12, 200319 DEPMOS Technology Simulation DEPMOS pixel array cuts through one cell Along the channel Perpendicular to the channel Metal 2 Metal 1 Oxyd Poly 2 Metal 2 Metal 1 Poly 2 Clear Gclear Channnel p Deep n n+ Deep p Poly 1

20 G.Lutz, RAL Sept.12, 200320 Pixel prototype production (6 wafer) for XEUS and LC (TESLA) Many test arrays - Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors Structures requiring only one metalization layer Production up to first metal layer finished Devices are under test Test results agree very well with device simulations

21 G.Lutz, RAL Sept.12, 200321 First DEPFET measurements on rectangular test transistors (W = 120µm L = 5µm) Output characteristics: Correct transistor behavior Transfer characteristics: Device can be completely switched off Transistor parameters agree with simulation

22 22 DEPFET test results: Noise and Spectroscopy Single circular DEPFET L = 5 µm, W = 40 µm time-continuous filter, τ = 6 µsec

23 G.Lutz, RAL Sept.12, 200323 Rectangular double cell test structure as used in TESLA pixel prototype

24 24 DEPFET test results Clearing of internal gate: complete clearing possible? At which voltage? Single rectangular DEPFET: measure current with cleared internal gate As function of clear voltage Measure pedestal noise Compare situation of charge generation followed by single clear pulse with many clear pulses before reading Single clear pulse Many clear pulses

25 G.Lutz, RAL Sept.12, 200325 TESLA Module concept with DEPFETs Sensor area thinned down to 50 µm Remaining frame for mechanical stability carrying readout and steering chips

26 G.Lutz, RAL Sept.12, 200326 Estimated Material Budget (1 st layer): Pixel area: 100x13 mm 2, 50 µm : 0.05% X 0 steer. chips: 100x2 mm2, 50 µm : 0.008% X 0 (massive) Frame :100x4 mm 2, 300 µm : 0.09% X 0 Module Concept reduce frame material!!! by etching of "holes" in the frame perforated frame: 0.05 % X 0 total: 0.11 % X 0 5-layer (CCD-like) layout for the vertex detector 1 st layer module: sensitive area 100x13 mm 2 sensitive area thinned down to 50 mm, supported by a directly bonded 300 mm thick frame of silicon readout chips steering chips

27 G.Lutz, RAL Sept.12, 200327 Top Wafer Handle Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer Processing thin detectors - the Idea -

28 G.Lutz, RAL Sept.12, 200328 Processing thin detectors - Direct Wafer Bonding - SOI Wafer prepared by MPI für Microstrukturphysik, Halle picture from: Q.-Y. Tong and U. Gösele Semiconductor Wafer Bonding John Wiley & Sons, Inc.

29 G.Lutz, RAL Sept.12, 200329 Direct Wafer bonding after Implantation Bonded wafers (structured implant through BOX): infrared transmission pictures from MPI Halle (M. Reiche) improve surface condition before bonding Direct Wafer Bonding possible, but some voids after annealing!

30 G.Lutz, RAL Sept.12, 200330 Anisotropic Wet Etching - TMAH - Tetra-Methyl-Ammonium-Hydroxide good selectivity to oxide almost perfect selectivity to Al no alkali ions poorer selectivity to (111) (30:1) rough surface after etching (hillocks) 54.72 deg

31 G.Lutz, RAL Sept.12, 200331 Diodes & Teststructures on thin Silicon * test bondability of implanted oxide & electrical performance of diodes on thin silicon * 2 types of thinned diodes n+n+ Al SiO 2 p+p+ unstructured n+ on top structured p+ in bond region 3 Wafers Type II: Implants like DEPFET config. * + 4 Wafers with standard Diodes as a reference * p+p+ Al n+n+ SiO 2 structured p+ on top unstructured n+ in bond region 3 Wafers Type I: Simplified standard technology guard ring

32 G.Lutz, RAL Sept.12, 200332 Diodes & Teststructures on thin Silicon - Type I: CV curves, full depletion voltage - 250 µm, standard diode, 10 mm 2 1/C 2 (10 -4 nF -2 ) bias voltage (V) C(V fd ) t = 46 m 50 µm, standard diode, 10 mm 2 1/C 2 (10 -4 nF -2 ) bias voltage (V)

33 G.Lutz, RAL Sept.12, 200333 Diodes & Teststructures on thin Silicon - Type I: IV curves - 250 µm, 4 standard diodes, 10 mm 2 50 µm, 4 standard diodes, 10 mm 2 bias voltage (V) reverse current (pA) 800..950 pA/cm 2 700..850 pA/cm 2 back side completely free

34 G.Lutz, RAL Sept.12, 200334 Diodes & Teststructures on thin Silicon - Type II: IV curves - contact opening and metallization after etching of the handle wafer reverse current (nA) Diodes of various sizes: 0.09 cm 2 – 6.5 cm 2 - no guard ring - - surface generated edge current included – reverse currents after annealing bias voltage (V) about 2V full depletion voltage about 1 nA/cm2 including edge generated current

35 G.Lutz, RAL Sept.12, 200335 Readout electronics for DEPFET pixels Developed in collaboration with other groups: XEUS: MPE,Jülich,Buttler TESLA: Bonn, Mannheim,MPI Driver chips : Switching Clearing Row selection Readout chips: Signal amplification Pedestal subtraction Zero suppression TESLA readout chip Current based readout

36 G.Lutz, RAL Sept.12, 200336 New steering chip I.Peric (Bonn), P.Fischer (Mannheim) AMS 0.8µm HV versatile sequencing chip (internal sequencer flexible pattern) high speed + high voltage range (20V) drives 64 DEPFET-rows (can be daisy chained) produced 12/2002 Switcher II: 4.6 mm 4.8 mm Results: power consumption: ~1W /channel tested ok to 30MHz

37 G.Lutz, RAL Sept.12, 200337 Current based Readout Storage phase: input and sample-switch closed : gate-capacitance of nmos charged I STORE Transfer phase: output switch closed : (done immediately after sampling) I STORE is flowing out Sampling phase: input and sample-switch opened : voltage at capacitance unchanged current unchanged I = I In + I Bias How to store a current ??

38 G.Lutz, RAL Sept.12, 200338 CURO - Architecture front end: automatic pedestal subtraction (double correlated sampling) - easy with currents - analog currents buffered in FIFO Hit-Logic performs 0 suppression and multiplexes hits to ADC (ADC only digitizes hits !) CURO : CUrrent Read Out

39 G.Lutz, RAL Sept.12, 200339 Results - CURO I (Marcel Trimpl, Bonn) TSMC 0.25µm, 5metal contains all blocks for a fast DEPFET R/O radiation tolerant layout rules with annular nmos produced 05/2002 CURO I: analog part (current memory cell): tested up to: 25MHz differential non-linearity: 0.1 % noise contribution to readout: < 39nA digital part: works with desired speed (50MHz) 4 mm 1.5 mm Crucial parts of readout work Design of CURO II submitted Delivery Dec.03 TESLA Goal: Thin fullsize pixel matrix 2005

40 G.Lutz, RAL Sept.12, 200340 Summary DEPFET structure invented 1984 Offers many unique features and applications Development in MPI Semiconductor Detector Laboratory with high-tech production technology in collaboration with other institutes DEPFET pixel detectors for X-ray astronomy (XEUS) Particle physics (TESLA) are major projects of the laboratory Other applications are also foreseen Development is progressing very well

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