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Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration.

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Presentation on theme: "Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration."— Presentation transcript:

1 Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration

2 Joel Goldstein, RALLCWS 3/05 2 Outline 1.Reminder: ILC Vertex Detector Column Parallel CCDs Conceptual Readout Scheme 2.First Generation Prototypes 3.Second Generation Prototypes

3 Joel Goldstein, RALLCWS 3/05 3 The Vertex Detector 5 layers (15-60mm) ~ 0.1% X 0 per layer 20 m 20 m pixels 800 million channels Background rates force readout –50 s for Layer 1 –250 s for Layer 2

4 Joel Goldstein, RALLCWS 3/05 4 Column Parallel CCDs Separate readout for each column Readout ASIC bump-bonded to CCD ASICs contain amplifiers, ADC and digital processing N+ 1 Column Parallel CCD Readout time = (N+1)/F out

5 Joel Goldstein, RALLCWS 3/05 5 Ladder Readout Layer 1 read out 20 times per bunch train 50k z pixels Layers 2-5 read out 5 times per bunch train 31k z pixels 4.4 GPixels in total Have to sparsify at front end

6 Joel Goldstein, RALLCWS 3/05 6 Detector Level DAQ Amplification ADC Filtering Clustering Multiplexer

7 Joel Goldstein, RALLCWS 3/05 7 Front End Readout Chain 1.3 million hits = 20 Mbytes per bunch train

8 Joel Goldstein, RALLCWS 3/05 8 First Prototype CPC/CPR Column parallel CCD principle proven Noise < 100 electrons Minimum clock ~1.9 V No sparsification in ASIC Charge Amplifiers (inverting) Voltage Amplifiers (non-inverting) 6 keV X-rays

9 Joel Goldstein, RALLCWS 3/05 9 Next Generation ASIC No major changes to amplifiers or ADC Digital cluster finding: –2x2 kernel –Extended cluster read out Expanded cluster to be read out 0000 0000 0000 0000 0000 0000 0000 0550 0000 0000000 0000000 0000000 0000000 0000000 0055000 0000000 Cluster found 0000000 0000000 000 000 000 000 000 000 000 000 000

10 Joel Goldstein, RALLCWS 3/05 10 CPR-2 Output Sparsification Cluster Binary 5-bit ADC Preamp Input & Multiplexing Finding Conversion DATA

11 Joel Goldstein, RALLCWS 3/05 11 CPR-2 IBM 0.25 m 6 x 9.5 mm Chips have arrived at RAL Stand alone testing starting Test features: –direct analogue I/O pads –I/O serial register between ADCs and cluster logic

12 Joel Goldstein, RALLCWS 3/05 12 Summary First generation CPCCD/ASIC tested Second generation ASIC ready for testing Cluster finding implemented Sparsification at front end –Major steps on road to ILC readout

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