1. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. Embedded Linux Conference 2008 Adding Framebuffer support to Freescale SoCs Apr 17, 2008 York Sun, Ben Eckermann Freescale Semiconductor

2. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2 Video to the Power of 5 ► 3 Planes of images Bottom plane: PowerPoint presentation Middle plane: 2 AOI (Areas of Interest) decoding video Top plane: 2 more AOI with 2 more videos Total of 5 AOI, all operating independently ► All running under Linux ® Mplayer for video decode (utilizing AltiVec™ technology)‏ Separate Linux Framebuffer per AOI ► DIU hardware acceleration Per-pixel alpha blending handled by DIU (hardware)‏ AOI Framebuffers have no concept of physical screen location or blending

3. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 3 MPC8610 Integrated Host Processor MPX Coherency Module MPX Bus DDR/DDR2 Memory Controller Enhanced Local Bus 2 x DUART 2 x I 2 C, 32 x GPIO SPI Timers Ext Interrupt 4 ch DMA x8 PCI Express® On-chip Switch 2 x SSI I 2 S/AC97 Audio LCD Controller x4 PCI Express® 4 ch DMA PCI On-chip Switch 32 KB I-Cache e600 Core 256 KB L2 32 KB D-Cache 2 x FIR/SIR IrDA Target Applications: Robotic vision and navigation Aerospace/defense display, control and image processing Kiosks with image processing Multi-function printers and scanners Single-board computers e600 Power Architecture™ CPU 667 MHz – 1.33 GHz e600 core 256 KB on-chip backside L2 Cache with ECC AltiVec® vector processor for image processing Double precision FPU, 4 x integer units Interfaces and Features DDR/DDR2 controller, 64/32-bit, 333-533 MHz (ECC)‏ LCD controller, 24 bit/pixel, 60 Hz refresh Up to SXGA (1280 x 1024) resolution 3 planes (XGA) + 1 cursor plane 2-I 2 S/AC97 audio ports 2-PCI-Express® (x1/x2/x4/x8; x1/x2/x4)‏ PCI 2.2, 32-bit, 33/66 MHz Enhanced local bus, 32-bit, to 133 MHz (ROM, NAND, NOR)‏ 2-I 2 C, 2-DUART, 4 channels each, 115 kb/s 2- Fast/Serial IrDA channels, 4 Mb/s 2-DMA, 4 channels each Serial peripheral interface (SPI), 4 to 16/32-bit characters 32-GPIO, 16 dedicated, 16 multiplexed Machine check external interrupt Watchdog and 2-global timers Power, Package, Technology, Schedule 15 W max at 1066 MHz, Tj=105C, 0.95V 11.5 W max at 667 MHz, Tj=105C, 0.95V 783 FC-PBGA, 90 nm SOI, RoHS compliant Rev 1.0 Samples 4Q-07, Production 1H-08 No known Export Restrictions for MPC8610, evaluation board or Linux® BSP freescale.com/imageprocessor

4. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 4 PCEVALHPCD-8610E Evaluation Platform Shipping Now! ► In the box ► MPC8610 development board board in chassis Preloaded latest Linux BSP Default settings  CPU at 1066 MHz  System at 533 MHz ► Cables 3-conductor power cord DB-9 RS-232 cable USB TAP  CWH-UTP-PPCC-HE ► CD with Hardware Design Workbook (131 pages)‏ ► Packing List ►On the web: freescale.com/imageprocessor ►More documentation ►Linux ® BSPs downloadable now

5. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 5 MPC8610 Key Features ► Image Processing e600 Power Architecture™ core with AltiVec™ Vector Processor ► 2D/3D Graphics Handling AltiVec™ Vector Processor Interface with external Graphics Processing Units (GPU)‏ ► Graphics Display Display Interface Unit ► Audio Inputs/Outputs Synchronous Serial Interface (SSI) for I 2 S/AC97 ► Memory IMEM/DMEM, L2 Cache, DDR1/DDR2, NAND, NOR, etc. DMA Controllers ► Additional Connectivity PCI and PCI Express® Interfaces Enhanced Local Bus Controller I 2 C Interfaces DUART Fast/Serial Infrared Interfaces (FIRI/SIRI)‏ Serial Peripheral Interface (SPI)‏ General Purpose I/O ► Interrupts and Timers Programmable Interrupt Controller (PIC)‏ Global Timer Module Watchdog Timer ► Low Power Consumption ► High Performance

6. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. MPC8610 Display Interface Unit (DIU)‏ LCD Controller

7. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 7 Multiple Graphics Layers

8. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 8 Graphics Subsystem DDR2 Memory LCD Display MPX Coherency Module MPX Bus DDR/DDR2 Memory Controller LCD Controller 32 KB I-Cache e600 Core 256 KB L2 32 KB D-Cache

9. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 9 DIU Modes of Operation- Mode 0 ► Mode 0: No Output DIU Plane 1 Plane 2 Plane 3 Memory Display Interface Unit (DIU)‏ Plane 1 Plane 2 Plane 3 2D/3D Graphics (CPU or GPU)‏ Video and/or graphic planes Graphics No Output

10. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 10 DIU Modes of Operation- Mode 1 ► Mode 1: All Planes Output to Display Panel DIU Plane 1 Plane 2 Plane 3 Memory Display Interface Unit (DIU)‏ Plane 1 Plane 2 Plane 3 2D/3D Graphics (CPU or GPU)‏ Video and/or graphic planes Graphics Plane 1 Plane 2 Plane 3

11. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 11 Plane 2 DIU Modes of Operation- Mode 2 ► Mode 2: Only Plane 1 Output to Display Panel DIU Plane 1 Plane 2 Plane 3 Memory Display Interface Unit (DIU)‏ Plane 1 Plane 2 Plane 3 2D/3D Graphics (CPU or GPU)‏ Video and/or graphic planes Graphics Plane 1 Plane 3

12. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 12 Plane 2 DIU Modes of Operation – Mode 3 ► Mode 3: Output All Planes to Memory DIU Plane 1 Plane 2 Plane 3 Memory Display Interface Unit (DIU)‏ Plane 1 Plane 2 Plane 3 2D/3D Graphics (CPU or GPU)‏ Video and/or graphic planes Graphics Plane 3 Plane 1

13. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 13 DIU Modes of Operation – Mode 4 ► Mode 4: Output Colorbar DIU Plane 1 Plane 2 Plane 3 Memory Display Interface Unit (DIU)‏ Plane 1 Plane 2 Plane 3 2D/3D Graphics (CPU or GPU)‏ Video and/or graphic planes Graphics

14. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 14 DIU: Pixel Structure Each pixel contains four elements: alpha, red (R), green (G) and blue (B)‏ RedGreenBlueAlpha 8 bits LSBMSBLSBMSBLSBMSBLSBMSB

15. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 15 Hardware Cursor ► A 32 x 32 pixel hardware cursor is stored in memory ► The cursor is laid on top of all three planes ► Each pixel in the cursor has the following 16-bit format:

16. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 16 Area Descriptors ► An area descriptor defines the specific region on a plane that will be displayed on the LCD panel Area Descriptors Specify: Pixel format Bitmap source size Area of interest size Bitmap source location Byte flip Image flip Chroma key

17. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 17 Software Components used on MPC8610HPCD DVI Encoder Application (MPlayer, etc.)‏ DIU Driver OS Framebuffer Linux ® OS LVDS Encoder (OR)‏

18. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 18 Software Components ► U-boot Initialize DVI encoder ► Linux ® Framebuffer Driver initializes device and associates with the kernel framebuffer  Sets AOIs, clock rates, memory addresses, area descriptor fields File system  /dev/fb Application

19. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 19 Initialization and Use Build components ► Enable the framebuffer code in the Linux ® kernel ► Enable DIU driver code in Linux kernel Boot and Use ► Probe for the device driver ► Initialize device 1. Allocate memory corresponding to the resolution chosen 2. Pixel format (size, position)‏ 3. AOI size and offset 4. Chroma keying 5. Gamma table 6. Cursor bitmap address and position 7. Background 8. Horizontal and vertical timing parameters 9. Interrupts 10. Pixel clock 11. Enable DIU ► Register with Linux framebuffer ► Change resolution (and corresponding timing parameters) using “fbset” fbset –a x -depth Picks up parameters from /etc/fb.modes ► Initial tests using fbv and MPlayer ► Custom applications to demonstrate AOIs and blending of planes

20. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 20 Initialization and Use

21. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 21 Initialization and Use ► For activity in multiple planes, create a minimum of 3 ADs For more, chain the ADs

22. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 22 Initialization and Use

23. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 23 Initialization and Use ► Supports 2 AOIs per plane Non-zero value for Next AD only for 1 st of the 2 AOIs

24. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 24 Display Interface Unit Capabilities ► Parallel TTL display interfaces ► Red/Green/Blue (RGB) and 256-level grayscale input pixel format 24 bits/pixel (bpp)‏ ► Programmable bit order definition up to 8 bits per component ► Hardware cursor 32 x 32 pixels, 16 bits/pixel ► Up to 256 levels α-blending ► Chroma keying selectable by range ► Independent programmable Gamma adjustments for each color component ► Memory write-back mode to store intermediate results, virtually extending the number of graphics planes ► 5 operating modes

25. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 25 Showtime! Demo on MPC8610HPCD

26. TM

27. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 27 Contact YorkSun@Freescale.com