1. Hussein Bin Sama && Tareq Alawneh
Finite State Machines
Presented by:
Hussein Bin Sama && Tareq Alawneh
Supervisor: Dr.Lo`ai Tawalbeh

2. Outlines FSM Introduction. FSM Design. VHDL Design of FSM.
FSM minimization.
Case Study.

3. FSM definition Finite state machine (FSM)
FSM is a model of behavior composed of a finite number of states, transitions between those states, and actions.

4. Concept of the State Machine
Computer Hardware = Datapath + Control
Datapath status
Registers
Combinational Functional
Units (e.g., ALU)
Busses
FSM generating sequences
of control signals
Instructs datapath what to
do next
Control
Control
State
Datapath
status
Control
Signal
Outputs
Datapath

5. Mealy vs. Moore State Machines
Finite State Machines (FSM) are of two types:
Moore Machines
Next State = Function(Input, Present State)
Output = Function(Present State)
Mealy Machines
Output = Function(Input, Present State)

6. Present State Register
Moore FSM
Output Is a Function of a Present State Only
Present State Register
Next State
Function
(comb. logic)
Output
Inputs
Present State
Outputs
clock
reset
transition
condition 1
state 1 /
output 1
state 2 /
output 2
transition
condition 2

7. Present State Register
Mealy FSM
Output Is a Function of a Present State and Inputs
Next State
Function
(comb. logic)
Output
Inputs
Present State
Outputs
Present State Register
clock
reset
transition condition 1 / output 1
state 1
state 2
transition condition 2 /
output 2

8. Moore FSM that Recognizes Sequence “10”
Moore FSM - Example
Moore FSM that Recognizes Sequence “10”
S0 / 0
S1 / 0
S2 / 1 1
reset

9. Moore FSM that Recognizes Sequence “10”
Mealy FSM - Example
Moore FSM that Recognizes Sequence “10”
0 / 0
1 / 0
1 / 0 S0 S1
reset
0 / 1

10. Moore and Mealy Machines
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
Same I/O behavior
Different # of states

11. Finite State Machine Word Problems
Finite String Pattern Recognizer
A finite string recognizer has one input (X)
and one output (Z ).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never been seen.

12. Finite State Machine Word Problems
Step 1. Understanding the problem statement
Sample input/output behavior: X: Z: X: Z:

13. Finite State Machine Word Problems
Finite String Recognizer
Step 2. Draw State Diagrams for the strings that must be
recognized. I.e., 010 and 100.
Reset S0
[0] 1
Moore State Diagram
Reset signal places
FSM in S0 S1 S4
[0]
[0] 1 S2 S5
[0]
[0]
0,1 S3 S6
Loops in State
Outputs 1
[1]
[0]

14. Finite State Machine Word Problems
Finite String Recognizer
Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = ..01 (state S2)
Reset S0
[0] 1 S1 S4
[0]
[0] 1 S2 S5
…01
[0]
[0] 1
0,1 S3 S6
…010
[1]
[0]
…100

15. Finite State Machine Word Problems
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
Reset S0
[0] 1 S1 S4 1
[0]
[0] …1 …0 1 S2 S5
…01
[0]
[0] 1 S3 S6
0,1
[1]
[0]
…010
…100

16. Finite State Machine Word Problems
Finite String Recognizer
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!

17. Finite State Machine Word Problems
Finite String Recognizer
Reset S0
[0] 1 S1 S4 1
[0]
[0] …1 …0 1 1
Final State Diagram S2 1 S5
…01
[0]
[0]
..10 1 S3 S6
0,1
[1]
[0]
…010
…100

18. Six Step Process FSM Design
1.Understand the statement of the Specification.
2.Obtain an abstract specification of the Synchronous Sequential Circuits (SSC).
3.Generate State Table.
4.Perform state minimization.
5.Choose FF types to implement SSC state register.
6.Implement the SSC.

19. Vending Machine Example

20. Vending Machine Example
Example: Vending Machine SSC
General Machine Concept:
Nickel = 5 cents
Dime = 10 cents
Machine needs 15 cents
to open
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
Vending
Machine
SSC N D
Reset
Clk
Open
Coin
Sensor
Gum
Release
Mechanism

21. Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
Nickel = 5 cents
Dime = 10 cents
Machine needs 15 cents
to open
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open
Initial Design

22. Vending Machine Example
Step 3: State Minimization
Present
State A B C D 1 X N
Inputs
Next
Output
Open
Reset N
N , D
[open] D A B C
Merge States which have the same output
S0=A
S1=B
S2+S3 = C
S4+S5+S6+S7+S8 = D
Minimized Design
Symbolic State Table

23. Vending Machine Example
Step 4: State Encoding
D1 D0
Next State
Q + 1 Q+
X X
X X
Present State Q D N
Inputs
Output
Open X
State A B C D
NOTE!
For D-FFs the next state will be what is at the D input.

24. Vending Machine Example
Step 5. Choose FFs for implementation
D FF easiest to use
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
Q1 Q0 00 D
D N Q1 N Q0 1 X 01 11 10
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates

25. VHDL Design of State Machines

26. FSM minimization Four steps for FSM minimization example.
Present State
Inputs
X=a
X=b
X=c A B C D E F
E,1
C,0
B,1
A,0
F,1
D,1
C,1
Next state , output
Step(1) Generate groups of states that generate the same output. This is called portions P1 = ( A,C) (B,D,E,F)

27. FSM minimization x A C B D E F a b c 2 2 1 1 1 1 1 1 2 2 2 2 2 2 2 1
Step(2) Create the following table based on step1 . Then generate the next partitions P2
Present State
Inputs
X=a
X=b
X=c A B C D E F
E,1
C,0
B,1
A,0
F,1
D,1
C,1
Next state , output x
Group #1
A C
Group #2
B D E F a b c
2 2
1 1
P2 = (A C)(B D E)(F)
Group Number

28. Note: P2 = P3 then stop partitions and go to step 4
FSM minimization
Step(3) Create the following table based on step2 . Then generate the next partitions P3
Present State
Inputs
X=a
X=b
X=c A B C D E F
E,1
C,0
B,1
A,0
F,1
D,1
C,1
Next state , output x
Group #1
A C
Group #2
B D E
Group #3 F
a b c
2 2
1 1 1 2
P3 = (A C)(B D E)(F) = P2
Note: P2 = P3 then stop partitions and go to step 4

29. FSM minimization Step(4) Renaming phase. New state name Old state name
(A,C)
(B,D,E) F
Present State
Inputs
X=a
X=b
X=c A B C D E F
E,1
C,0
B,1
A,0
F,1
D,1
C,1
Next state , output
Present State
Inputs
X=a
X=b
X=c S1 S2 S3
S2,1
S1,0
S3,1
S1,1
Next state , output

30. Case Study: FSMD: finite-state machine with datapath
Example : ( greatest common divisor )
(c) state diagram
(a) black-box view
(b) desired functionality
y = y -x 7:
x = x - y 8:
6-J:
x!=y 5:
!(x!=y)
x<y
!(x<y) 6:
5-J: 1: 1 !1
x = x_i 3:
y = y_i 4: 2:
2-J:
!go_i
!(!go_i)
d_o = x
1-J: 9:
0: int x, y;
1: while (1) {
2: while (!go_i);
3: x = x_i;
4: y = y_i;
5: while (x != y) {
6: if (x < y)
7: y = y - x;
else
8: x = x - y; }
9: d_o = x;
go_i
GCD
x_i
y_i
Steps :
First create algorithm
Convert algorithm to “complex” state machine
Known as FSMD: finite-state machine with datapath
d_o

31. Creating the datapath Create a register for any declared variable
Create a functional unit for each arithmetic operation
Connect the ports, registers and functional units
y = y -x 7:
x = x - y 8:
6-J:
x!=y 5:
!(x!=y)
x<y
!(x<y) 6:
5-J: 1: 1 !1
x = x_i 3:
y = y_i 4: 2:
2-J:
!go_i
!(!go_i)
d_o = x
1-J: 9:
subtractor
7: y-x
8: x-y
5: x!=y
6: x<y
x_i
y_i
d_o
0: x
0: y
9: d
n-bit 2x1
x_sel
y_sel
x_ld
y_ld
x_neq_y
x_lt_y
d_ld
< !=
Datapath

32. Creating the controller’s FSM
y = y -x 7:
x = x - y 8:
6-J:
x!=y 5:
!(x!=y)
x<y
!(x<y) 6:
5-J: 1: 1 !1
x = x_i 3:
y = y_i 4: 2:
2-J:
!go_i
!(!go_i)
d_o = x
1-J: 9:
y_sel = 1
y_ld = 1 7:
x_sel = 1
x_ld = 1 8:
6-J:
x_neq_y 5:
!x_neq_y
x_lt_y
!x_lt_y 6:
5-J:
d_ld = 1
1-J: 9:
x_sel = 0 3:
y_sel = 0 4: 1: 1 !1 2:
2-J:
!go_i
!(!go_i)
go_i
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Controller
Same structure as FSMD
subtractor
7: y-x
8: x-y
5: x!=y
6: x<y
x_i
y_i
d_o
0: x
0: y
9: d
n-bit 2x1
x_sel
y_sel
x_ld
y_ld
x_neq_y
x_lt_y
d_ld
< !=
Datapath

33. Splitting into a controller and datapath
go_i
Controller implementation model
y_sel
x_sel
Combinational logic Q3 Q0
State register
go_i
x_neq_y
x_lt_y
x_ld
y_ld
d_ld Q2 Q1 I3 I0 I2 I1
Controller !1
0000 1:
subtractor
7: y-x
8: x-y
5: x!=y
6: x<y
x_i
y_i
d_o
0: x
0: y
9: d
n-bit 2x1
x_sel
y_sel
x_ld
y_ld
x_neq_y
x_lt_y
d_ld
< !=
(b) Datapath 1
!(!go_i)
0001 2:
!go_i
0010
2-J:
x_sel = 0
x_ld = 1
0011 3:
y_sel = 0
y_ld = 1
0100 4:
x_neq_y=0
0101 5:
x_neq_y=1
0110 6:
x_lt_y=1
x_lt_y=0 7:
y_sel = 1
y_ld = 1 8:
x_sel = 1
x_ld = 1
0111
1000
1001
6-J:
1010
5-J:
1011 9:
d_ld = 1
1100
1-J:

34. Areas of possible improvements
Optimizing the FSMD
Areas of possible improvements
merge states
states with constants on transitions can be eliminated, transition taken is already known
states with independent operations can be merged

35. Optimizing the FSMD (cont.)
original FSMD
optimized FSMD
y = y -x 7:
x = x - y 8:
6-J:
x!=y 5:
!(x!=y)
x<y
!(x<y) 6:
5-J: 1: 1 !1
x = x_i
y = y_i 4: 2:
2-J:
!go_i
!(!go_i)
d_o = x
1-J: 9:
int x, y; 3:
int x, y;
eliminate state 1 – transitions have constant values 2:
go_i
!go_i
x = x_i
y = y_i
x<y
x>y
y = y -x
x = x - y 3: 5: 7: 8:
d_o = x 9:
merge state 2 and state 2J – no loop operation in between them
merge state 3 and state 4 – assignment operations are independent of one another
merge state 5 and state 6 – transitions from state 6 can be done in state 5
eliminate state 5J and 6J – transitions from each state can be done from state 7 and state 8, respectively
eliminate state 1-J – transition from state 1-J can be done directly from state 9

36. Optimizing the datapath
Sharing of functional units
if same operation occurs in different states, they can share a single functional unit
Multi-functional units
ALUs support a variety of operations, it can be shared among operations occurring in different states

37. Optimizing the FSM State minimization (As Discussed Previously)
task of merging equivalent states into a single state
state equivalent if for all possible input combinations the two states generate the same outputs and transitions to the next same state

38. References
“Embedded Systems Design: A Unified Hardware/Software Introduction” Book Slides. Frank Vahid, Tony Givarrgis, Wiley, 2002
“Digital Design with CPLD Applications & VHDL” Book,Dueck , 2005
“Advanced Topic on Sequential Logic Design” handout.