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Recent Development of FinFET Technology for CMOS Logic and Memory

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Presentation on theme: "Recent Development of FinFET Technology for CMOS Logic and Memory"— Presentation transcript:

1 Recent Development of FinFET Technology for CMOS Logic and Memory
Chung-Hsun Lin EECS Department University of California at Berkeley

2 Outline Why FinFET Recent FinFET Develop Memory Conclusion
FinFET process Unique features of FinFET Mobility, workfunction engineering, corner effect, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29

3 The Power5 microprocessor
MOSFET Scaling ITRS 2001 Projection The first transistor 1947 The Power5 microprocessor Technology Scaling Investment Market Growth Better Performance/Cost Same transistor design concept NTUEE Seminar 2006/04/29

4 Scaling : Moore’s law Technology Drivers Reduced cost / function
Improved performance Greater circuit functionality Source: Intel NTUEE Seminar 2006/04/29

5 Bulk-Si MOSFET Scaling Issues
Leakage current is the primary barrier to scaling To suppress leakage, we need to employ: Higher body doping  lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric  higher gate leakage Ultra-shallow S/D junctions  higher Rseries G S D Desired characteristics: - High ON current (Idsat) - Low OFF current Substrate Gate Source Drain Leff Nsub Xj Lg Tox courtesy of Prof. Kuroda Keio University NTUEE Seminar 2006/04/29

6 Issues for Scaling Lg to <25 nm
VT variation (statistical dopant fluctuations) Leakage Incommensurate gains in Idsat with scaling limited carrier mobilities parasitic resistance NTUEE Seminar 2006/04/29

7 Advanced MOSFET Structures
Leakage can be suppressed by using a thin body Ultra-Thin Body Gate Silicon Substrate Source Drain TBOX TSi SiO2 SOI Double Gate Source Drain Gate 1 Vg Tox TSi SOI Gate 2 NTUEE Seminar 2006/04/29

8 Thin-Body MOSFETs Control short-channel effects with Tbody
No channel doping needed! Relax gate oxide (Tox) scaling Double-Gate is even more effective Scalable to 10nm gate lengths Buried Oxide Substrate Source Drain Gate Gate Source Drain Tbody Ultra-Thin Body Double-Gate NTUEE Seminar 2006/04/29

9 Electric Field Reduction
Reduced vertical field in DG and UTB No doping = No Qdepl! Expected to benefit: Mobility Gate Leakage Gate Qinv Qdepl Bulk Gate Buried Oxide Substrate Qinv Thin-Body NTUEE Seminar 2006/04/29

10 Thin-Body MOSFETs Control short-channel effects with Tbody
No channel doping needed! Relax gate oxide (Tox) scaling  Ion  Cload Double-Gate is even more effective Scalable to 10nm gate lengths Potentially less Vt scatter (dopant fluctuation) Improved mobility Lower vertical electric field No impurity scattering Improved swing Better control of SCE Lower VT No depletion or junction capacitance NTUEE Seminar 2006/04/29

11 Circuit level benefits
50 35 25 18 Tbody,UTB = 5nm < 5nm Thin body devices Good control of SCE Steep Sub-threshold swing Higher Idsat Lower Capacitance - No Cjunc and Cdepl Better CV/I delay at lower power Source: Leland Chang NTUEE Seminar 2006/04/29

12 Double-Gate MOSFETs Planar DG MOSFET Vertical DG MOSFET FinFET Gate 1
Current flow S Planar DG MOSFET D Vertical DG MOSFET S D Current flow Gate 1 Gate 2 FinFET S D Current flow Gate 1 Gate 2 NTUEE Seminar 2006/04/29

13 Planar DG-FET 90° Rotation FinFET
Multi-Gate FinFET Drain Gate Source Source Drain Gate Gate Gate Source Drain Gate Drain Drain Planar DG-FET 90° Rotation FinFET Rotation allows for self-aligned gates Layout similar to standard SOI FET NTUEE Seminar 2006/04/29

14 Poly Gate Deposition/Litho
FinFET Process Flow Si Fin SiO2 Resist BOX Poly SOI Substrate Fin Patterning Poly Gate Deposition/Litho Si3N4 Spacer NiSi Gate Etch Spacer Formation S/D Implant + RTA Silicidation NTUEE Seminar 2006/04/29

15 FinFET Device Structure
Source Gate Drain All features defined by optical lithography and aggressive trimming NTUEE Seminar 2006/04/29

16 10nm FinFET TEM NiSi Poly-Si 220Å SiO2 cap Lg=10nm Si Fin BOX
NTUEE Seminar 2006/04/29

17 10nm FinFET I-V Dual N+/P+ poly gates: - Need VT control Low DIBL
NMOS: 120 mV/V PMOS: 71 mV/V Good SCE despite thick Tox (27Å EOT) & Wfin (26nm) - Due to large S/D doping gradient & spacer thickness NTUEE Seminar 2006/04/29

18 Short-Channel Effects
Acceptable DIBL and subthreshold slope down to below 20nm Lgate Nearly ideal (60mV/dec) subthreshold slope at long Lgate NMOS better than PMOS due to slower As diffusion NTUEE Seminar 2006/04/29

19 Orientation <100> (110) Surface (110) (100) ~(111) (110)
<110> (110) Surface Gate Source Drain (110) (100) ~(111) (110) Rotation by 45º changes orientation from (110) to (100) Intermediate rotation similar to (111) NTUEE Seminar 2006/04/29

20 How Mobility Changes By shifting away from (100):
e is degraded, h is enhanced Can we benefit from changing the N/P ratio? NTUEE Seminar 2006/04/29

21 Gate Delay PMOS enhancement (20%) is larger than NMOS degradation (8%)
Net delay improvement Trade off h and e NOR: PMOS stack h very important Most improvement NAND: NMOS stack h less important Least improvement Lgate=35nm h, e NOR Inv NAND (100) (111) (110) (100) NMOS (110) PMOS NTUEE Seminar 2006/04/29

22 Optimized FinFET (110) PMOS (100) NMOS
Gate Source Drain Gate Source Drain (110) PMOS (100) NMOS Trade off layout area for performance NTUEE Seminar 2006/04/29

23 FinFET Layout Area Non-(100) orientation saves area
Inverter Non-(100) orientation saves area Higher PMOS Idsat reduces drawn W 45º orientation is less area efficient for smaller W These devices are small anyway…does it matter? Use only in critical path? NTUEE Seminar 2006/04/29

24 Hybrid-Orientation-Technology (HOT)
Super HOT: SOI version DSB: bulk version NTUEE Seminar 2006/04/29

25 VT: What CMOS Needs… Need symmetrical VT’s for proper CMOS operation
Need low VT’s for speed Inverter Response VDD VIN= VTN VIN= VDD-VTP Output VDD Input NTUEE Seminar 2006/04/29

26 Gate Work Function Single gate material VTn = -VTp = 0.4V N+/P+ Poly
For low body doping, desired FM values are: ~ 4.5 eV for NMOS ~ 5.0 eV for PMOS Need two separate work functions for NMOS and PMOS! NTUEE Seminar 2006/04/29

27 Molybdenum FM Engineering by Ion Implantation
Anneal time = 15m except for 900oC (15s) TMo = 15nm FM can be lowered by N+ implantation and thermal anneal DFM increases with dose energy (N segregates to SiO2 interface & forms Mo2N) P. Ranade et al., IEDM 2002 NTUEE Seminar 2006/04/29

28 Mo-Gated FinFETs (PMOS)
Y.-K. Choi et al., IEDM 2002 Vt shift Lg=80nm, TSi=10nm Vds=0.05V |Vt|=0.2V for lightly doped body, and is adjustable by N+ implantation Alternative technique: Full silicidication (NiSi) of n+/p+ Si gates (J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002) Potential issues include: - dopant penetration - thermal stability - stress/adhesion - gate dielectric reliability NTUEE Seminar 2006/04/29

29 Corner Effect in Triple or More Gates
Different Vth at corner region Significant subthreshold leakage current Strong corner radius, body doping dependence B. Doyle et al., VLSI Tech., p. 133, 2003 NTUEE Seminar 2006/04/29

30 Corner Effect [1] DESSIS 3-D device simulator
Vg=0.2 V Vg=1 V z z S D G y y 2D current density distribution 2D current density distribution DESSIS 3-D device simulator Ideal rectangular fin shape Nsub=1e15cm-3 NTUEE Seminar 2006/04/29

31 Corner Effect [2] Nsub=5e18cm-3 corner flat Vg=0.2 V Vg=1 V
z corner y flat Vg=0.2 V 2D current density distribution z y Vg=1 V 2D current density distribution NTUEE Seminar 2006/04/29

32 3D Simulation w/ Various Shape of Corner
Lg=1mm, Wsi=30nm, Hsi=30nm, Tox=1nm R=0, 5, 10, 15m NTUEE Seminar 2006/04/29

33 Short Channel Behavior
MG device with sharp corner shows better short channel behavior than the rounded corner NTUEE Seminar 2006/04/29

34 Double-humps induced by cap transistor
30x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3 Cap transistor induced lower Vt is very significant. It may attribute to thicker Tox, and more partial depleted. NTUEE Seminar 2006/04/29

35 Volume Inversion [1] Gate Gate Gate Gate eDensity eDensity 6.1E+13 6.1E+13 5.3E+13 5.3E+13 T T si 4.5E+13 si 4.5E+13 3.6E+13 3.6E+13 2.8E+13 2.8E+13 2.0E+13 2.0E+13 N =10 15 cm -3 N =10 18 cm -3 sub sub Oxide Oxide The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left). NTUEE Seminar 2006/04/29

36 Volume Inversion [2] For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region. The inversion charge (current) in the subthreshold region is proportional to Tsi. NTUEE Seminar 2006/04/29

37 QM Surface Potential Correction
Undoped case NTUEE Seminar 2006/04/29

38 I-V Verification Model can predict both subthreshold and strong inversion region well. NTUEE Seminar 2006/04/29

39 S/D Series Resistance Issue
J. Kedzierski et al., IEDM 2001 S/D series resistance will degrade the performance of thin body device Can be improved by the selective Si epitaxy raised S/D NTUEE Seminar 2006/04/29

40 Outline Why FinFET Recent FinFET Develop Memory Conclusion
FinFET process Unique features of FinFET Mobility, workfunction engineering, corner effect, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29

41 Triple-Gate Transistor
B. Doyle et al., VLSI Tech. 2003 NTUEE Seminar 2006/04/29

42 Omega-Gate Transistor
NTUEE Seminar 2006/04/29

43 5nm Nanowire FinFET NTUEE Seminar 2006/04/29

44 Independent Gate FinFET
Control the threshold voltage Ideal rectangular shape of Si fin NTUEE Seminar 2006/04/29

45 Independent Gate FinFET
NTUEE Seminar 2006/04/29

46 Multi-Channel FinFET NTUEE Seminar 2006/04/29

47 Metal Gate FinFET NTUEE Seminar 2006/04/29

48 Metal-Gate FinFET Vth adjustment Improvement of Ion
K.G. Anil et al., VLSI Tech. 2005 NTUEE Seminar 2006/04/29

49 TiN/HfO2 FinFET Vth adjustment Reduce Gate leakage
N. Collaert et al., VLSI Tech. 2005 NTUEE Seminar 2006/04/29

50 Inverted T Channel (ITFET)
L. Mathew et al., IEDM 2005 UTB + FinFET Continuous effective width NTUEE Seminar 2006/04/29

51 Strained FinFET 25% drain current enhancement of PFET by introducing recessed Si0.8Ge0.2 S/D Compressive stress and raised S/D P. Verheyen et al., VLSI 2005 NTUEE Seminar 2006/04/29

52 Impact of Gate-Induced Strain
MuGFETs with TiSiN gate (+3GPa stress as deposited) Eeff=0.4MV/cm Stress [MPa] Mobility Enhancement [%] σxx σyy σzz (100) NMOS (110) NMOS (100) PMOS (110) PMOS Experiment 4 59 8 10 Inverse PR Model -540 -290 -1900 -1 NTUEE Seminar 2006/04/29

53 Issue of Fin Formation K. Endo et al., IEDM 2005 Neutral beam etching can accomplish damage (defect) free fabrication of high aspect ratio fin. Higher mobility is obtained in NB device due to atomically-flat surface NTUEE Seminar 2006/04/29

54 Sidewall Spacer Transfer (SWT) Process
Both gate and fin are formed by SWT SiN is selected as hard mask material for Si RIE on top of fin Can be used as the CMP stopper during poly gate planarization (important for gate SWT) Suppress the agglomeration of Si fin during selective Si epi Prevent the leakage of the top corner Used as RIE stopper in the gate RIE process A. Kaneko et al., IEDM 2005 NTUEE Seminar 2006/04/29

55 SWT Process The threshold voltage uniformities for SWT FinFETs of 15nm fin and 15nm gate length over the wafer is better than ArF and EB lithography NTUEE Seminar 2006/04/29

56 Selective Gate Sidewall Spacer Formation
NTUEE Seminar 2006/04/29

57 FinFET on Bulk Si Substrate
Bulk FinFET has the advantages of cheaper wafer cost, ease of combination with conventional bulk CMOS. K. Okano et al., IEDM 2005 NTUEE Seminar 2006/04/29

58 Characteristics of Bulk FinFET
Better subthreshold swing Better short channel control Negligible body effect T. Park et al., VLSI 2003 NTUEE Seminar 2006/04/29

59 Outline Why FinFET Recent FinFET Develop Memory Conclusion
FinFET process Unique features of FinFET Mobility, workfunction engineering, corner effect, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29

60 DRAM application of Bulk FinFET
NTUEE Seminar 2006/04/29

61 DRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT NTUEE Seminar 2006/04/29

62 NWL Scheme Lower VT (doping concentration) FinFET combined with NWL scheme can provide lower leakage and higher performance NWL bias is critical to refresh fail bit NTUEE Seminar 2006/04/29

63 SONOS Application of FinFET
J. Hwang et al., TSMC 2005 High Performance FinFET SONOS flash cells with gate length of 20nm is demonstrated. Program/erase window of 2V with high P/E speed (Tp=10ms, TE=1ms) NTUEE Seminar 2006/04/29

64 SONOS Application of FinFET
Excellent endurance: up to 10K P/E cycles Good retention: 1.5V after 10years retention time J. Hwang et al., TSMC 2005 NTUEE Seminar 2006/04/29

65 FinFETs based 6-T SRAMs pulldown access load Large fraction of the total chip area will be memory1 Leakage problem Limited by impact of variations General-Purpose Architectures for Media Processing and Database Workloads, Parthasarathy Ranganathan Thesis, current processor designs often devote the largest fraction of on-chip transistors (up to 80%) to caches FinFETs offer good control of short channel effects 1Source : Ranganathan, 2000 NTUEE Seminar 2006/04/29

66 Static Noise Margin The minimum noise voltage at the storage node needed to flip the state Large SNM is desirable Make pulldown device stronger relative to access transistor Source: Bhavnagarwala, 2001 NTUEE Seminar 2006/04/29

67 SNM spread with variations
Thicker Si body better Higher performance due to Rs limitations Greater noise immunity (SNM) Lesser spread in SNM Taurus Device Simulation NTUEE Seminar 2006/04/29

68 SNM spread with variations
To improve SNM Wpulldown  - 2 fins Laccess  meff, pulldown>meff, access (100)pulldown device (110) access device Taurus Device Simulation NTUEE Seminar 2006/04/29

69 FinFET Circuit design tradeoffs
Advantages Excellent SCE control Scalability Double-gates are self-aligned Insensitivity to channel doping Limitations Gate material Contact/Series resistance Area efficiency (fin pitch) Back gate routing NTUEE Seminar 2006/04/29

70 Conclusion Unique FinFET physics are introduced.
Recent developing effort on FinFET technology are discussed Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET FinFET based CMOS and memory cells are very promising for sub-32 technology node. NTUEE Seminar 2006/04/29

71 Thank you very much for your attention
NTUEE Seminar 2006/04/29

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