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Designing a Fast and Reliable Memory with Memristor Technology
Manjunath Shevgoor, Rajeev Balasubramonian, Naveen Muralimanohar University of Utah, HP Labs Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Background Store data in the form of resistance Metal oxide sandwiched between two electrodes Inherently non conducting Creation of conductive Filaments of oxygen vacancies reduces resistance Source: Cong Xu et al., Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture, ASPDAC 2014 Designing a Fast and Reliable Memory with Memristor Technology
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Voltage Dependent Resistance
The resistance of a ReRAM cell is not constant but varies with the applied voltage Kr(p, V ) = p * R(V/p)/R(V ) R(V/p) and R(V ) are the equivalent resistance of the cell biased at V/p and V Kr is the non-linearity. Eg: if Kr=20, resistance increases 10x when voltage is halved Resistance decreases with increasing voltage Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Bit Line Word DRAM Cell Word Line Bit Memristor Cell Bit Line Word PCM Cell Cell Size of 4F2 Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Cross Point Structure Driver Transistors Selected Cell Mem- ristor Selector Memristor Cell Because of non-linearity, it is possible to select a cell without an access transistor. Arrays can be layered vertically without resorting to 3D stacking. Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Reading and Writing 0V Vdd/2 Selected Cell Sneak Current Vdd Half Selected Cells Driver Transistors Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Bit Lines RW RW RW V Word Lines VW1 VW2 VWN RW RW RW VWN1 RW RW RW V/2 RW RW RW VWNM V/2 V/2 Bit Line Mux Bit line and word line resistances eat into the cell Voltage Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Effects of Ileak Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Effects of Ileak Decreases Voltage at selected cell Increases Write Latency Can cause Write Failure Distorts bit line current Increases read complexity Decreases read margin Designing a Fast and Reliable Memory with Memristor Technology
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Sneak path currents can distort Iread
Vread Iread Vread/2 Ileak Vread/2 Ileak Vread/2 Ileak Vread/2 Vread/2 Vread/2 Sneak path currents can distort Iread Designing a Fast and Reliable Memory with Memristor Technology
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Step 1: Read background current (Ileak)
Vread/2 Ileak Vread/2 Ileak Vread/2 Ileak Vread/2 Ileak Vread/2 Vread/2 Vread/2 Step 1: Read background current (Ileak) Designing a Fast and Reliable Memory with Memristor Technology
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Step 2: Read total Vread current (Iread)
Ileak Vread/2 Ileak Vread/2 Ileak Vread/2 Vread/2 Vread/2 Step 2: Read total Vread current (Iread) Designing a Fast and Reliable Memory with Memristor Technology
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State of selected cell determines Iread ~ Ileak
tBG_READ tREAD Read Latency Designing a Fast and Reliable Memory with Memristor Technology
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Proposal 1: Re-use value in sample and hold circuit
Vread Vread/2 Pprech Pacc Vr S2 Sensing Circuit S1 Sample and Hold Sneak Current Proposal 1: Re-use value in sample and hold circuit Designing a Fast and Reliable Memory with Memristor Technology
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Reusing Sneak Current Read
Rows Sneak Current uA Columns Designing a Fast and Reliable Memory with Memristor Technology
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Re-Use Sneak Current Reading for the same Column
tBG_READ tREAD tREAD Read Latency1 Read Latency2 Designing a Fast and Reliable Memory with Memristor Technology
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Impact of Cell Location
Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Word Line Drivers Bit Line Mux Longer write latencies Increased error rates Designing a Fast and Reliable Memory with Memristor Technology
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Array 1 Array 2 Array 3 Array 512 Bit 1 Bit 2 Bit 3 Bit 512 64 Byte Cache line Default Mapping Leads to some lines with high error rate Designing a Fast and Reliable Memory with Memristor Technology
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Proposal 2: Stagger the array mapping
Cacheline 1 Cacheline 2 Cacheline 3 Cacheline 4 1 2 3 Nth bit in cacheline Array 0 Array 1 Array 2 Array 3 Default Mapping 1 3 2 Proposed Mapping Designing a Fast and Reliable Memory with Memristor Technology
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Proposal 2: Impact on Write Latency
1 2 3 Nth bit in cacheline Array 0 Array 1 Array 2 Array 3 Default Mapping 1 3 2 Proposed Mapping Designing a Fast and Reliable Memory with Memristor Technology
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Proposal 3: Compress to reduce write latency
Array 1 Array 2 Array 3 Array 512 Bit 1 Bit 2 Bit 3 Bit 512 64 Byte Cache line 1 3 2 Proposed Mapping With 50% Compression Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Conclusions With great density come a few challenges Sneak Currents limit array size, complicate reads, and delay writes Affect reliability Background current can be reused Reliability can be improved at the cost of write latency Compression can reduce write latency 13% performance improvement 30X reduction in multi bit error probability Work in progress Designing a Fast and Reliable Memory with Memristor Technology
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Designing a Fast and Reliable Memory with Memristor Technology
Thank You Designing a Fast and Reliable Memory with Memristor Technology
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