1. Jean-Marie Bussat – October 16, 20151 FPPA2000 Bias generator

2. Jean-Marie Bussat – October 16, 20152 Requirements FPPA98 was a prototype  All bias currents and voltage references were external  The circuit was packaged in a big 80 pins package. FPPA2000 should be "production ready" and should save space on the VFE board to allow integration of 5 channels on a final size board.  Number of pins should be reduced (to use a smaller package)  "Services" should be integrated:  To minimize the number of external components.  To be less sensitive to environment.  To be less sensitive to ageing and radiation damages.

3. Jean-Marie Bussat – October 16, 20153 Requirements (cont) Bias currents:  Preamplifier: 400µA  Slow control: 100µA  FPU analogic: 200µA  FPU digital:100µA  Logic:100µA  Output buffer:100µA Voltage references:  Preamplifier:2.2V (baseline shift compensation)  Amplifiers:2V(amplifiers clamp)  Slow control:2.4V(temperature measurement) 0.5V(output offset) 1.2V(temperature measurement)  FPU analogic:2.0V(switches clamp) 0.7V(switches clamp) 2.1V(comparator threshold)  Output buffer:3.3V(ADC "offset")

4. Jean-Marie Bussat – October 16, 20154 Bias generator block diagram Bias generator needs a radiation hard, temperature compensated, stable voltage or current reference.  use the ADC voltage reference (2.4V) for that purpose Idea behind this choice: The ADC do its conversion relatively to its reference voltage. If this voltage changes (radiation damage or ageing) and the ADC input voltage also changes by the same amount, the conversion result will remain unchanged.  The "operating point" of the FPPA has to be indexed to the ADC reference voltage Bias currents : For each cell requiring a bias current, multiple copies have to be distributed  A lot of transistors are needed for this purpose but available space is limited.  Instead of distributing currents directly, we are distributing voltages that are images of the bias currents (detailed explanation follows)

5. Jean-Marie Bussat – October 16, 20155 Bias generator block diagram (cont) Reference voltage sources Main current source I V Secondary current sources vcc "signal" ADC 2.4V voltage reference REXT ADREF AGND Bias decoupling 12KΩ 200µA

6. Jean-Marie Bussat – October 16, 20156 Bias Generator: simplified schematic voltage references Matched resistor network (matching = 0.5%) Open-loop gain large enough to ensure a good precision on reference voltages. Error dominated by resistor matching  Gain  46dB

7. Jean-Marie Bussat – October 16, 20157 Bias Generator: simplified schematic current sources Loop closed to minimize current mirror errors. (reduces radiation damage sensitivity) Matched resistors Size ratio defines bias current Ir Ic Ratio of Ir (current reference) and Ic (current copy) dominated by resistor matching and OPamp. offset.

8. Jean-Marie Bussat – October 16, 20158 Voltage reference OPamp. Design goals: - as simple as possible - high open-loop gain - low output resistance - unity gain stable Low impedance output stage Prevent V CE from being greater than V CEBO

9. Jean-Marie Bussat – October 16, 20159 Voltage reference OPamp. (cont.) open-loop gain Open-loop gain: 56dB GBW product:64MHz Phase margin:107°

10. Jean-Marie Bussat – October 16, 201510 Voltage reference OPamp. (cont.) PSRR -2V +5V Power supply rejection ratio > 15dB between 1Hz and 30MHz > 30dB between 1Hz and 30MHz

11. Jean-Marie Bussat – October 16, 201511 Current source OPamp. Prevent V CE from being greater than V CEBO

12. Jean-Marie Bussat – October 16, 201512 Current source OPamp. (cont.) open-loop gain Open-loop gain: 56dB GBW product:1GHz (uncompensated) Phase margin:45° (uncompensated)

13. Jean-Marie Bussat – October 16, 201513 Current source OPamp. (cont.) PSRR -2V +5V Power supply rejection ratio > 70dB between 1Hz and 30MHz > 35dB between 1Hz and 30MHz

14. Jean-Marie Bussat – October 16, 201514 Bias generator PSRR -2V +5V between 1Hz and 30MHz > 28dB (voltages) > “82dB" (currents) > 4dB (voltages) > “79dB" (currents)

15. Jean-Marie Bussat – October 16, 201515 Inter-bias rejection Bias generator Sources simulating the loads  Inject noise here Look at the effects here Between 1Hz and 30MHz: Rejection > 140dB (currents) > 110dB (voltages)

16. Jean-Marie Bussat – October 16, 201516 Startup Check for oscillations when power is turned on Check that the generator doesn't latch in an unwanted state Check settling time of currents and voltages Bias Generator response to a 1µs step on both power supplies (+5V and -2V)

17. Jean-Marie Bussat – October 16, 201517 Layout (FPPA2000) Bias current sources Digital bias Voltage references

18. Jean-Marie Bussat – October 16, 201518 Layout (FPPA2001) Current source for preamplifier removed No other schematic change Layout reorganized to be more space efficient Power supplies routing improved Buffer moved Space occupied by PA bias