1. Chapter 3 Arithmetic for Computers
授課教師: 張傳育 博士 (Chuan-Yu Chang Ph.D.)
Tel: (05) ext. 4337

2. Introduction 自然數字的二進位表示法 負數表示法 二進位數的邏輯運算 (and, or)
二進位與十進位的轉換(binary to decimal conversion)
二進位與十六進位的轉換(binary to hexadecimal conversion)
十六進位與十進位的轉換
負數表示法
二進位數的邏輯運算 (and, or)
二進位數的算術運算(+, -, *, /)
分數(fraction)及浮點表示法
硬體如何實際執行加、減、乘、除。

3. Signed and Unsigned Numbers
In any number base, the value of ith digit d is
Binary numbers (base 2) least significant bit: the rightmost bit most significant bit: the leftmost bit decimal: n-1
Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number
How do we represent negative numbers? i.e., which bit patterns will represent which numbers?

4. Example: ASCII Vs. Binary Numbers
What is the expansion in storage if the number 1 billion is represented in ASCII versus a 32 bit integer?
1 billion = (10個ASCII符號) 1 ASCII = 8 bits 所以需要8*10=80 bits 因此80/32=2.5

5. Possible Representations of Negative Numbers
Sign and Magnitude: One's Complement Two's Complement 000 = = = = = = = = = = = = = = = = = = = = = = = = -1
Issues: number of zeros, ease of operations
Which one is best? Why?
The drawbacks of the sign-magnitude representation:
It’s not obvious where to put the sign bit.
Adders for sign and magnitude may need an extra step to set the sign because we can’t know in advance what the proper sign will be.
Two zeros, positive and negative zero.

6. MIPS: 2’s complement
以0為前導的數為正值
32 bit signed numbers: two = 0ten two = + 1ten two = + 2ten two = + 2,147,483,646ten two = + 2,147,483,647ten two = – 2,147,483,648ten two = – 2,147,483,647ten two = – 2,147,483,646ten two = – 3ten two = – 2ten two = – 1ten
maxint
minint
以1為前導的數為負值

7. Example: Binary to Decimal conversion
What is the decimal value of this 32-bits two’s complement number? (2)

8. Two's Complement Operations
Negating a two's complement number: invert all bits and add 1
Converting n bit numbers into numbers with more than n bits:
MIPS 16 bit immediate gets converted to 32 bits for arithmetic
copy the most significant bit (the sign bit) into the other bits > >
"sign extension"
lbu: load byte unsigned
lb: load byte

9. Signed versus Unsigned Comparison
MIPS offers two versions of the set on less than comparison
有號數的若小於則設定(slt, slti): set on less than, set on less than immediate
無號數的若小於則設定(sltu, sltiu): set on less than unsigned, set on less than immediate unsigned
範例．
假設暫存器 $s0 含有以下的二進位數
而暫存器 $s1含有以下的二進位數
經由以下兩個指令運算後，暫存器 $t0及 $t1 的值為何？
slt $t0, $s0, $s1
sltu $t1, $s0, $s1
解答 $s0: signed=-1, unsigned= $s1: signed=1, unsigned=1
得到 $t0 = 1 及 $t1 = 0.

10. Example : Negation Shortcut
Negate 2(10), and then check the result by negating -2(10).
2(10) =
Negating this number by inverting the bits and adding one = -2
= 2 +
0變1，1變0 +

11. Example Sign Extension Shortcut
Convert 16-bit versions of 2 and -2 to 32-bit binary numbers.
The 16-bit binary version of the number 2 is 2 =
Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word
The 16-bit binary version of the number -2 is -2 =
Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word

12. Binary-to-Hexadecimal Shortcut
Convert the following hexadecimal and binary numbers into the other base. (a) ECA8 6420(16) (b) (2)
E = = 1 C = = 3 A = = 5 8 = = 7 6 = = 9 4 = = B 2 = = D 0 = = F =>(a) =>(b) 13579BDF

13. Addition & Subtraction
Just like in elementary school (carry/borrow 1s)  
Two's complement operations easy
subtraction using addition of negative numbers x – y = x + (-y)
Example: = ? Solution: 0110=>1001+1=

14. Addition & Subtraction (cont.)
Overflow (result too large for finite computer word):
e.g., adding two n-bit numbers does not yield an n-bit number  0001 note that overflow term is somewhat misleading, it does not mean a carry “overflowed”

15. Detecting Overflow
No overflow when adding a positive and a negative number
No overflow when signs are the same for subtraction
Overflow occurs when the value affects the sign:
overflow when adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive and get a negative
or, subtract a positive from a negative and get a positive
Effects of Overflow (2’s complement)
An exception (interrupt) occurs
Control jumps to predefined address for exception
Interrupted address is saved for possible resumption
MIPS has two kinds of arithmetic instructions to recognize the 2’s complement and unsigned integer.
add, addi, and sub cause exceptions on overflow.
addu, addiu, and subu do not cause exceptions on overflow.

16. Overflow conditions for addition and subtraction
operation
Operand A
Operand B
Result
Indicating overflow
A+B
>=0
<0
A-B

17. Logical Operations
Shifts
邏輯左移指令 (sll) shift left logical： R形態格式
邏輯右移指令 (srl) shift right logical： R形態格式
範例： 假如暫存器 $s0 內容為 而指令 sll $t2, $s0, 8 被執行 $t2的值將為多少？
解答 上述指令的機器語言為： sll $t2, $s0, 8 10 16 8
unused

18. Logical Operations bit-by-bit And (and) 指令 and, andi
bit-by-bit Or (or) 指令
Or, ori
Example: Mask (遮罩)
如果暫存器 $t2 內含
而暫存器 $t1 內含
則在 MIPS 指令執行後
and $t0, $t1, $t2 #reg $t0 = reg $t1 & reg $t2
$t0 的值將會是
在 MIPS 指令執行後
or $t0, $t1, $t2 #reg $t0 = reg $t1 | reg $t2 5

19. Multiplication More complicated than addition
accomplished via shifting and addition
More time and more area
Let's look at 3 versions based on grade school algorithm (multiplicand) __x_ (multiplier)
Negative numbers: convert and multiply
there are better techniques, we won’t look at them

20. First Version of the Multiplication Algorithm
第一版乘法運算的演算法及硬體
乘積暫存器先預設為 0。
如果每個步驟須花費一個時脈週期，
這一版的乘法運算就要花費100
個時脈週期才能完成。
相當於以手算方式進行， 被乘數(multiplicand)每次往左移1bit， 乘數(multiplier)每次往右移1bit。

21. Multiplication
Example: First Multiply Algorithm
Fig 4.27

22. Second Version 第二版乘法運算的演算法及硬體 32-位元ALU 乘積暫存器先預設為 0。
在直式的乘法運算中， 每次乘積均會產生一個部份積；
因此，將目前的部份積左移一位， 相當於將前一部份積往右移一位。
優點：
只需右移電路。
被乘數暫存器只需32bit。
ALU只需32bit。

23. Final Version
優點：
乘數暫存器併入乘積暫存器的右半段。
省掉multiplier暫存器及右移電路。

24. Example
0010x0011

25. Multiplying Negative Numbers
Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer
Solution 2
Booth’s algorithm

26. Comparison of Multiplication of Unsigned and Twos Complement Integer
部分積以2n bit表示
可解決被乘數為負值的問題，但若乘數為負值時，仍無解
0011 (+3) x (-7) (+27)

27. Booth’s algorithm 令a為乘數(multiplier)，b為被乘數(multiplicand)
Booth’s algorithm的動作可表示成(ai-1-ai) 其中上式值的意義如下： 0 : do nothing +1 : add b -1 : subtract b
將被乘數相對於乘積暫存器往左移，相當於乘以2的冪次方，因此Booth’s algorithm可寫成下式的乘積項和
將上式整理可得
而且a-1=0，因此(1)式可改寫成 1 ai
ai-1
operation
Do nothing
Add b
Subtract b
a的2補數

28. Example: Booth’s Algorithm
2*-3 = 0010 * 1101
Iteration
Step
Multiplicand
Product
Initial values
0010 1
10=>prod=prod-Mcand
Shift right Product 2
01=>prod=prod+Mcand 3 4
11=> no operation

29. Booth’s Algorithm

30. Examples Using Booth’s Algorithm

31. Examples Using Booth’s Algorithm (cont.)

32. Division
More complex than multiplication
Based on long division

33. Division of Unsigned Binary Integers
Quotient
Divisor
1011
Dividend
1011
001110
Partial
Remainders
1011
001111
1011
Remainder
100

34. First Version of the Division Algorithm
每一次演算法需移動被除數往右1bit。
所以，將被除數放在64bit的左半部，
餘數暫存器初值設為除數。

35. Example : First Divide Algorithm
初值是被除數的值
Using a 4-bit version of the algorithm to calculate 7/2
Iteration
Step
Quotient
Divisor
Remainder
Initial values
0000 1
Rem=Rem-Div
Rem<0,+Div, sll Q Q0=0
Shift Div right 2 3 4
Rem>=0, sll Q, Q0=1
0001 5
0011

36. Second version of the Division Algorithm
第一版的除法器中，
除數暫存器最多只有一半的位元是有用的，因此可將ALU寬度減半
將餘數左移一位元相當於將除數右移一位元

37. Third version of the Division Algorithm餘數 商
藉由同時將運算元和商同時移位來加速除法運算。

38. Example : Third Divide Algorithm
Using a 4-bit version of the algorithm to calculate 7/2
Iteration
Step
Divisor
Remainder
Initial values
0010
Shift Rem left 1 1
Rem=Rem-Div
Rem<0,+Div, sll R, R0=0 2 3
Rem>=0, sll R, R0=1 4 5

39. Floating Point (a brief look)
We need a way to represent
numbers with fractions, e.g.,
very small numbers, e.g.,
very large numbers, e.g., ´ 109
Representation:
sign, exponent, significand: (–1)sign * significand * 2exponent
more bits for significand gives more accuracy
more bits for exponent increases range
IEEE 754 floating point standard:
single precision: 8 bit exponent, 23 bit significand
double precision: 11 bit exponent, 52 bit significand

40. Floating Point Sign bit Biased Significand or Mantissa Exponent
+/- .significand x 2exponent
Point is actually fixed between sign bit and body of mantissa
There is one bit to the left of the radix point.
Exponent value is biased representation
A fixed value is subtracted from the field to get the true exponent value
The bias equals (2k-1-1)

41. IEEE 754 floating-point standard
Leading “1” bit of significand is implicit
Exponent is “biased” to make sorting easier
all 0s is smallest exponent all 1s is largest
bias of 127 for single precision and 1023 for double precision
summary: (–1)sign * (1+significand) * 2exponent – bias
Example:
decimal: = -3/4 = -3/22
binary: = -1.1 x 2-1
floating point: exponent = 126 =
IEEE single precision:

42. IEEE 754 Formats

43. IEEE 754 floating-point standard
Example: Show the IEEE 754 binary representation of the number (10) in single and double precision
Solution: = -(0.11) = -(1.1)2 * 2-1 single precision ： … (126)10 double precision ： … (1022)10

44. Example 1
(a) Convert the decimal number -1.5 to a 32-bit floating-point number with IEEE 754 format. (b) Convert a 32-bits IEEE 754 format floating-point number 43A0C000 to the decimal number.
Solution:
(a) 1.5=1.12=1.1* S=1, C=E+127=127= , F= (b)43A0C000= S=0, C= =135=E+127, =>E=8, F= *28= = 321.5

45. Example 2 What decimal number is represented by this word?
Solution: 符號位元為-1，指數欄位為129，有效數字欄位為1.01。

46. IEEE 754單精密度表示 指數值介於1到254之間 -126~127 指數和假數都是0的情況，可視符號位元分成正零和負零。
+0 :
-0 :
指數全為1，假數全為0時，視符號位元代表正負無限大。
+∞ :
-∞ :
指數全為1，假數部分為非0，則表示Not a Number, NaN
正規化的非零值：
(-1)s * 1.F * 2e-127

47. Example 3
(a) What are the smallest negative number, largest negative number, smallest positive number and the largest positive number for 32 bit normalized floating-point number.
(b) What would be the range of exponential digit can represent in the IEEE 754 format?
Solution: (a) 最小的指數為:-126 最大的指數為:127 最小的假數為: 最大的假數為: 所以 最大正值: *2127 最小正值:1.0*2-126 最小負值: *2127 最大負值:- 1.0*2-126 (b) -126~127

48. Floating-Point Arithmetic +/-
Check for zeros
Align significands (adjusting exponents)
Add or subtract significands
Normalize result
Round the number

49. Example:
Assume that we can store four decimal digits of the significand and two decimal digits of the exponent x x10-1
Step 1: x 10-1= x 101
Step 2: Addition of the significands = The sum is x 101
Step 3: Normalization x 101= x 102
Step 4: Round the number x 102

50. Floating-Point Addition
浮點數加法運算
範例．
試著將 0.5 和 以二進位方式進行加法運算
解答．
0.5 = (0.1)2
= (1.0)2 * 2-1
= - (0.0111)2
= - (1.11)2 * 2-2
步驟 1. 比較兩個數的指數， 將指數大小調到與較大者相同：
- (1.11)2 * 2-2 = - (0.111)2 * 2-1
步驟 2. 將兩數之有效數字相加：
(1.0)2 * (0.111)2 * 2-1 = (0.001)2 * 2-1
步驟 3. 將總和正規化：
(0.001)2 * 2-1 = (1.0)2 * 2-4
步驟 4. 將結果四捨五入

51. Floating-Point Arithmetic x/
Check for zero
Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
Round the number
The sign of the result depends on the signs of the original operands.
All intermediate results should be in double length storage

52. Floating Point Multiplication

53. Floating Point Multiplication
0.5*
Solution: 0.5= 0.1(2) =1.0* = (2) = -1.11*2-2
Step 1: adding the exponents = =124
Step 2: Multiplying the significand * 1.11 = * 2-3
Step 3 :Rounding the product * 2-3
Step 4 :Check the sign * 2-3 =

54. Floating Point Complexities
Operations are somewhat more complicated (see text)
In addition to overflow we can have “underflow”
Accuracy can be a big problem
IEEE 754 keeps two extra bits, guard and round
four rounding modes
positive divided by zero yields “infinity”
zero divide by zero yields “not a number”
other complexities
Implementing the standard can be tricky
Not using the standard can be even worse
see text for description of 80x86 and Pentium bug!

55. Accurate Arithmetic
若兩個值進行運算，若要減去某較小值時，需進行指數部分的對齊，因此須對significand進行右移，進而造成有效位元的損失。
在運算過程中，significand通常儲存在較長的register，因此，回存到floating-point格式時，會損失ㄧ些額外的位元。
所以需要guard和round等兩個位元。

56. The use of guard bits X = 1.00…00x21, Y = 1.11…11x 20 =0.11…11x21
Y會損失ㄧ個bit
Y會損失ㄧ位數
加入4個guard bits
加入2個guard bits

57. Rounding with Guard Digits
Add 2.56x100 to 2.34x102, assuming that we have three significant decimal digits. Round to the nearest decimal number with three significant decimal digits.
Solution
2.56 x 100 = x 102
2.34 x 102
Round bit
Guard bit
Without guard and round digits

58. Chapter Three Summary
Computer arithmetic is constrained by limited precision
Bit patterns have no inherent meaning but standards do exist
two’s complement
IEEE 754 floating point
Computer instructions determine “meaning” of the bit patterns
Performance and accuracy are important so there are many complexities in real machines (i.e., algorithms and implementation).
We are ready to move on (and implement the processor) you may want to look back (Section 4.12 is great reading!)

59. Floating-point Arithmetic
A FP operation may produce one of these conditions:
Exponent overflow
Exponent underflow
Significand underflow
Significand overfolw

60. Appendix

61. Example: C Bit Fields
The following C code allocates three fields with a word labeled receiver: a 1-bit field named ready, a 1-bit field named enable, and an 8-bit field named receivedByte. It copies receivedByte into data, set ready to 0, and sets enable to 1. int data; struct { unsigned int ready: 1; unsigned int enable: 1; unsinged int receivedByte: 8; } receiver; … data = receiver. receivedByte; receiver.ready = 0; receiver. Enable = 1; What is the compiled MIPS code? Assume data and receiver are allocated to $s0 and $s1.

62. Example: C Bit Fields (Answer)
The field look like this in a word
Solution 1: sll $s0, $s1, 22 #move 8-bit field to left end srl $s0, $s0, 24 #move 8-bit field to right end andi $s1, $s1, 0xFFFE #bit 0 set to 0 ori $s1, $s1, 0x0002 #bit 1 set to 1
Solution 2: srl $s0, $s1, 2 andi $s0, $s0, 0x00FF 31 10 9 2 1
receivedByte
enable
ready

63. Review: Boolean Algebra & Gates
Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true
Show the truth table for these three functions.
Show the Boolean equations for these three functions.
Show an implementation consisting of inverters, AND, and OR gates.

64. An ALU (arithmetic logic unit)
Let's build an ALU to support the andi and ori instructions
we'll just build a 1 bit ALU, and use 32 of them

65. Review: The Multiplexor
Selects one of the inputs to be the output, based on a control input
Lets build our ALU using a MUX: S C A B 1
note: we call this a 2-input mux
even though it has 3 inputs!

66. 1-bit logical unit for AND and OR

67. Different Implementations
Let's look at a 1-bit ALU for addition: a 1 b
CarryIn
Sum
CarryOut
Inputs
Outputs
cout = a b + a cin + b cin
sum = a xor b xor cin

68. Building a 32 bit ALU
The adder created by directly linking the carries of 1-bit adders is called a ripple carry adder.

69. What about subtraction (a – b) ?
Two's complement method: just negate b and add.
How do we negate?
Invert each bit and then add 1
A 1-bit ALU that performs AND, OR and addition on a and b or a and b:
減法如同對運算元的反相值做加法運算而且最低有效位元本身還是有個進位輸入訊號
a + (¬b) + 1 = a + (-b) = a - b
減法運算 ALU 0: Operation = 2, Binvert = 1, 及 CarryIn = 1 ALU 1-31: Operation = 2 及 Binvert = 1

70. Tailoring the ALU to the MIPS
Need to support the set-on-less-than instruction (slt)
remember: slt is an arithmetic instruction
produces a 1 if rs < rt and 0 otherwise
use subtraction: (a-b) < 0 implies a < b
Need to support test for equality (beq $t5, $t6, $t7)
use subtraction: (a-b) = 0 implies a = b

71. Supporting slt Can we figure out the idea?
bit 0的電路圖，以bit 31的set值作為less的輸入
bit 31的電路圖，以+結果的符號位元值，作為set的值。
Set=1表結果為負值=> a<b。
Set=0表結果為正值=> a>b。

72. 支援 小於即設定 (slt)指令
範例： slt $t0, $s1, $s2
ai： 暫存器 $s1的位元 i
bi：暫存器$s2的位元 i
結果： 假如 $s1 < $s2 0…001
否則 0…000
32位元 ALU
觀察：假如 $s1 - $s2 <0,
則 $s1 < $s2
結果 0 = 加法器的符號位元
控制訊號 / 輸入
Operation = 3
Less 1-31 = 0
Binvert = 1
CarryIn 0 = 1
Less 0 = Set

73. Constructing an ALU 支援條件分支指令 假使兩個暫存器相等或假使不相等時作分支 觀察
if a=b then a-b = 0
if a-b = 0 then
Result = 0…00
Zero = 0 不等時
Zero = 1 相等時

74. Constructing an ALU
The value of the three ALU control line and the corresponding ALU operation
Operation
Bnegate
CarryIn
Bnegate 1
Operation 00 01 10 11
and or
add
subtract
set on less than
Function
Result
Less
CarryOut

75. ALU Symbol

76. Conclusion We can build an ALU to support the MIPS instruction set
key idea: use multiplexor to select the output we want
we can efficiently perform subtraction using two’s complement
we can replicate a 1-bit ALU to produce a 32-bit ALU
Important points about hardware
all of the gates are always working
the speed of a gate is affected by the number of inputs to the gate
the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)

77. Problem: ripple carry adder is slow
Is a 32-bit ALU as fast as a 1-bit ALU?
Is there more than one way to do addition?
two extremes: ripple carry and sum-of-products
Can you see the ripple? How could you get rid of it?
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1b1 c2 =
c3 = b2c2 + a2c2 + a2b2 c3 =
c4 = b3c3 + a3c3 + a3b3 c4 =
Not feasible! Why?

78. Carry-lookahead adder
An approach in-between our two extremes
Motivation:
If we didn't know the value of carry-in, what could we do?
When would we always generate a carry? gi = ai bi
When would we propagate the carry? pi = ai + bi
Did we get rid of the ripple?
c1 = g0 + p0c0
c2 = g1 + p1c1 c2 =
c3 = g2 + p2c2 c3 =
c4 = g3 + p3c3 c4 = Feasible! Why?

79. Carry-lookahead adder
全加器的進位可表示成
以簡潔的符號表示成
寫成通式

80. Carry-lookahead adder
因此進位輸入可表示成
使用4位元加法器為基本單位

81. Carry-lookahead adder
四位元 ALU進位公式

82. Use principle to build bigger adders
Can’t build a 16 bit adder this way... (too big)
Could use ripple carry of 4-bit CLA adders
Better: use the CLA principle again!