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1 EGRE 254 Digital Logic Design Lecture 1 Dr. Jerry H. Tucker.

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1 1 EGRE 254 Digital Logic Design Lecture 1 Dr. Jerry H. Tucker

2 2 Web page Class handouts, announcements, and other information will be posted on the class web page at egre254/index.html. egre254/index.html Bookmark and monitor this page! There is a link to it on my home page which you can find by doing a Google search for Jerry Tucker.

3 3 Labs Everyone needs to be registered for Lab. –Either the 2:00 or 4:00 sessions on Thursday. –Due to the class size the lab will actually be divided into three sections, however, you must be registered for the original official time. –Normally lab will be in room 237, but occasionally may be in room 337. –Monitor the class web page for changes in lab location if there is no announcement go to room 237. –Lab report guidelines are posted on the class web page. –Not all labs will require a lab report. –Most labs will be conducted with a partner. –You should select a lab partner by next week.

4 4 Textbook We will use Digital Design Principles and Practices either 3 rd or 4 th editions by John Wakerly. The book may contain a CD with Xilinx software. This software is obsolete. Don’t bother to install it. You may want to go to dex.htm register and download and install the free ISEWebPack and the ModelSim MXE simulator on your home computer. You may also want to download and install the evaluation version of Orcad form form.aspx?dl=orcadDemo We will use this software in some labs.

5 5 Final course grades will be determined as follows: Homework10% Laboratory10% Quizzes (2)50% Final exam30% Some curving may be used to determine the final letter grade for this class. You may expect the grade dividing points to be as follows: Between A and B: 90-93. Between B and C: 80-85. Between C and D: 70-75. Between D and F: 60-65. The grade dividing points on the curve will be determined primarily by gaps in the distribution of the final average. It is not predetermined that a certain number of students will receive a given grade.

6 6 Digital logic design (DLD) In this class take time to understand the fundamental concepts and don’t get behind. If you do this, DLD will be an easy and interesting course. Digital systems are simpler and better behaved that analog systems. (Provided you follow the rules.) This is because in digital systems we deal with only two levels referred to as “0” and “1”. –Sometimes the “0” level is referred to as “false” and the “1” lever as true. –In logic circuits voltages levels correspond to the “0” and “1”. Typical “0” is a voltage near 0 volts, and “1” is a higher voltage such as 5 volts.

7 7 Digital Circuits Digital Circuits are divided into two major classifications. Combinational –Consist of logic gates with no feedback. –Output depends only on present input. Sequential –Contain flip-flops or gates with feedback. –Output depends on both present input and previous inputs. –Sequential circuits have memory.

8 8 We will typically use NAND gates and the 74LS logic family. All other gates can be implemented using NAND gates. 74LS gate outputs can drive about twenty 74LS inputs. In practice you probably should not drive much more that ten inputs.

9 9 0.0 V

10 10

11 11 Interfacing to non 74LS devices. Consider driving an LED. Or Dose it make any difference? I OH = -0.4 ma max I OL = 4.0 ma max for 74 I OL = 8.0 ma max for 54

12 12 Operating region

13 13

14 14 Pin count as seen from the top. Notice notch!

15 15 Field Programmable Gate Arrays (FPGA’s) may contain the equivalent of millions of gates in one IC.

16 16

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