1. UTA Noise and Reliability Laboratory 1 Md Mazhar Ul Hoque Advisor: Prof. Zeynep Celik-Butler Department of Electrical Engineering University of Texas at Arlington Noise and Reliability in Advanced Bipolar Technologies

2. UTA Noise and Reliability Laboratory 2 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

3. UTA Noise and Reliability Laboratory 3 Current BJT low-frequency noise models Gummel-Poon: VBIC – Flicker noise due to IBE, IBEP MEXTRAM: MODELLA:

4. UTA Noise and Reliability Laboratory 4 Importance and motivation Only one single noise source in base current: S IB =KF.I B AF. Noise in base current dominant only for higher base series resistance. Does not include any geometry, temperature or process parameter. Noise in collector current and internal resistances are neglected. Noise in collector current contributes at lower base series resistance. Noise from internal resistance contributes at higher bias current. To model all possible noise sources in advanced bipolar transistors: Noise in base current, collector current and internal resistances. Developing physics based scalable equations for the noise sources: Incorporating geometry, temperature and process dependant parameters. Writing computer source code for device and circuit analysis CAD tools to incorporate all possible noise sources in BJT. Research goal: Limitations in existing noise models:

5. UTA Noise and Reliability Laboratory 5 Polysilicon emitter bipolar transistors: 2 nd generation BiCMOS technology, Texas Instruments Inc. NPN and PNP transistors. Variable size, variable IFO thickness. SiGe heterojunction bipolar transistors: 1 st generation BiCMOS technology, National Semiconductor Corporation. NPN transistors. Variable size, variable design rules. Variable doping in base and collector. Advanced bipolar technologies under investigation

6. UTA Noise and Reliability Laboratory 6 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

7. UTA Noise and Reliability Laboratory 7 100K 4.8V R S R L 12V (a) (b) Collector-base measurement setup

8. UTA Noise and Reliability Laboratory 8 If has the dominant contribution, Collector-base measurement for unity coherence:

9. UTA Noise and Reliability Laboratory 9 Dominant noise source 0.7x100 μm 2 NPN, thickest IFO, R S =1MΩ0.7x100 μm 2 PNP, thickest IFO, R S =1MΩ Calculated S VC /S VB considering S IB contribution dominant closely matches experimental S VC /S VB ; SIB contribution dominant.

10. UTA Noise and Reliability Laboratory 10 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

11. UTA Noise and Reliability Laboratory 11 Area dependence of S IB in NPN transistors Noise source homogeneously distributed underneath the emitter. [ Darby Lan ]

12. UTA Noise and Reliability Laboratory 12 Internal emitter resistance and ideality factor of base current 0.7x100 μm 2 NPN, thickest IFO, R S =1MΩ m g mi (ohm -1 )

13. UTA Noise and Reliability Laboratory 13 Base current dependence diffusion fluctuation in emitter. tunneling fluctuation in IFO. recombination fluctuation in emitter- base space charge region. recombination fluctuation at spacer oxide interface. Emitter perimeter dependence Noise source distributed homogeneously around the emitter. Recombination fluctuation at the spacer oxide interface. Emitter area dependence Noise source distributed homogeneously underneath the emitter. Diffusion fluctuation in emitter or tunneling fluctuation in IFO. Physical origin of S IB

14. UTA Noise and Reliability Laboratory 14 Unity ideality factor of negligible. negligible. Physical origin of S IB (cont.)

15. UTA Noise and Reliability Laboratory 15 Diffusion and tunneling fluctuation component of S IB 0.7x100 μm 2 NPN, medium IFO, R S =1MΩ

16. UTA Noise and Reliability Laboratory 16 Area dependence of tunneling fluctuation of S IB in PNP transistors Tunneling-fluctuation source homogeneously distributed underneath the emitter. Thickest oxide Smaller device-dimension severely affected by lateral diffusion and mask undercut; effective emitter area considered.

17. UTA Noise and Reliability Laboratory 17 WmWm WpWp L 0 x1x1 x2x2 x3x3 base mono- silicon oxide Poly- silicon metal contact carrier concentration p(x) s ox sm sm p(x) α m, D m αp, Dpαp, Dp Diffusion fluctuation in S IB α m : Hooge parameter in mono-Si α p : Hooge parameter in poly-Si Assumption: α m = α p =α

18. UTA Noise and Reliability Laboratory 18 Tunneling fluctuation in S IB oxide permittivity barrier height for the minority carriers modified Planck’s constant area of IFO loss tangent of the oxide tunneling probability of minority carriers fluctuation in effective mass of minority carriers electronic charge Boltzmann constant IFO thickness

19. UTA Noise and Reliability Laboratory 19 Scaling effect on S IB RelativeAF IFO thickness 0.7x100 ( μ m 2 ) 0.7x0.7 ( μ m 2 ) thickest1.121.89 medium1.232.09 thinnest1.01 Diffusion fluctuation dominant in large (0.7x100μm 2 ) devices. Tunneling fluctuation dominant in small (0.7x0.7μm 2 ) devices. AF for S IB in PNP transistors

20. UTA Noise and Reliability Laboratory 20 Scaling effect on S IB in PNP transistors with thickest IFO Total S IB Tunneling fluctuation component of S IB Diffusion fluctuation component of S IB

21. UTA Noise and Reliability Laboratory 21 Poly-Si emitter oxide dldl dsds mono-Si emitter d l < d s Large device small device base Thicker polysilicon in smaller transistors. Lower dopant concentration; shallower junction. higher chance for minority carriers from base to reach and tunnel through the oxide interface; tunneling fluctuation dominant. FLUORINE EFFECT: fluorine enhances oxide break-up. lower fluorine (from BF 2 ) concentration causes less oxide breakup in smaller PNP devices; increased tunneling: (no fluorine in the transistors studied here) Emitter plug effect in smaller device

22. UTA Noise and Reliability Laboratory 22 Poly-Si emitter oxide d1d1 d 1 < d 2 base d2d2 mono-Si emitter Polysilicon surface almost perpendicular to wafer surface at emitter window sidewall. Reduced doping concentration in the perimeter region. Shallower junction close to emitter window perimeter. An overlap of the emitter-base space charge region with poly-mono silicon interface might occur close to perimeter. Perimeter depletion effect

23. UTA Noise and Reliability Laboratory 23 Perimeter/area vs. emitter area emitter area (μm 2 ) Perimeter/area For smaller transistors perimeter/area ratio increases sharply. non ideal peripheral component of base current increases. fluctuation in non-ideal base current might become significant. Perimeter depletion effect in smaller transistors

24. UTA Noise and Reliability Laboratory 24 Effect of IFO on DC characteristics of 0.7x100μm 2 NPN transistors IFO increases the current gain significantly.

25. UTA Noise and Reliability Laboratory 25 Effect of IFO on DC characteristics of 0.7x100μm 2 PNP transistors No significant improvement in current gain with increasing IFO thickness.

26. UTA Noise and Reliability Laboratory 26 Effect of interfacial oxide on S IB in NPN and PNP transistors 0.7x100 μm 2 NPN 0.7x100 μm 2 PNP IFO increases S IB both in NPN and PNP transistors.

27. UTA Noise and Reliability Laboratory 27 In PNP, diffusion fluctuation in mono and poly-silicon emitter dominates; less effect of IFO. In NPN, both diffusion fluctuation in mono and poly- silicon emitter, and tunneling fluctuation through IFO contribute. Difference in the effect of IFO in NPN and PNP transistors 0.7x100μm 2 transistors Device typeAF PNP~ 1 NPN~ 1.5

28. UTA Noise and Reliability Laboratory 28 Physics behind difference in NPN and PNP transistors Hole barrier height larger than electron barrier height at interfacial oxide: minority carriers (holes) severely suppressed in NPN; significant current gain improvement. minority carriers (electrons) not suppressed significantly in PNP; little current gain improvement. Effect of fluorine: fluorine accelerates oxide break-up. fluorine from emitter dopant BF 2 in PNP creates more oxide breakup; reduced tunneling and increased diffusion through broken oxide. Increased oxide breakup and faster diffusion of boron makes the emitter deeper in PNP : increased recombination-base current, reduced current gain improvement. higher diffusion fluctuation in larger monosilicon emitter region. Different oxidation rate of the base material could create different IFO thickness for NPN and PNP transistors on the same wafer.

29. UTA Noise and Reliability Laboratory 29 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

30. UTA Noise and Reliability Laboratory 30 0.7x100 μm 2 NPN 0.7x100 μm 2 PNP Effect of interfacial oxide on S IC IFO increases S IC both in NPN and PNP transistors.

31. UTA Noise and Reliability Laboratory 31 Some researchers assign the same origin of S IB to S IC. is merely an amplified S IB. S IC modeling Number fluctuation in S IC requires further investigation. carrier transport determined by electric field in base collector junction. Hooge type fluctuation at the collector side of base- collector junction. 1.E-07 1.E-06 1.E-05 1.E-041.E-03 I C (A) output conductance h 22 (ohm ) ~ I C (0.98) K=0.98 0.7x100μm 2 PNP, thickest IFO

32. UTA Noise and Reliability Laboratory 32 n(x) α, D Diffusion fluctuation in S IC saturated drift velocity WBWB collector 0 base mono- silicon oxide Poly- silicon metal contact carrier concentration n(x)

33. UTA Noise and Reliability Laboratory 33 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

34. UTA Noise and Reliability Laboratory 34 Effect of bias on coherence in NPN and PNP transistors 0.7x100 μm 2 NPN, thickest IFO, R S =1MΩ 0.7x100 μm 2 PNP, thickest IFO, R S =1MΩ Coherence decreases with increasing bias in NPN transistor.

35. UTA Noise and Reliability Laboratory 35 Effect of varying base bias resistance (R S ) on S V 0.7x100 μm 2 NPN, thickest IFO, IB=384nA S VC does not decrease any more for R S smaller than 1 kΩ. S VB becomes comparable to system background noise for R S smaller than 10 kΩ.

36. UTA Noise and Reliability Laboratory 36 4.8V 12V 1K 100K RSRS RLRL S VE S VC RERE Collector-emitter measurement setup

37. UTA Noise and Reliability Laboratory 37 0.7x100 μm 2 NPN, thickest IFO, R S =100Ω Dominant noise source in collector-emitter measurement Unity coherence. One single dominant noise source: S IC or S Vr ?

38. UTA Noise and Reliability Laboratory 38 S IC in collector-emitter measurement 0.7x100 μm 2 NPN, R S =100Ω no physical explanation for such high current dependence: SPURIOUS?

39. UTA Noise and Reliability Laboratory 39 0.7x100 μm 2 NPN, R S =100Ω Effect of interfacial oxide on S Vr

40. UTA Noise and Reliability Laboratory 40 Effect of internal resistance in collector-emitter measurement 0.7x100 μm 2 NPN, thickest IFO Collector-base measurement, RS=1MΩCollector-emitter measurement, RS=100Ω

41. UTA Noise and Reliability Laboratory 41 Tunneling fluctuation through interfacial oxide tunneling probability of the majority carriers through IFO fluctuation in base mono- silicon oxide Poly- silicon metal contact fluctuation in minority carrier tunneling fluctuation in majority carrier tunneling

42. UTA Noise and Reliability Laboratory 42 Interfacial oxide thickness RelativeEmitter areainterfacial oxide thickness (Å) from IFO thickness (μm2)(μm2) minority carrier majority carrier fluctuation (S IBT )fluctuation (S Vre ) PNPNPN 0.7x10014.50 4.08 thickest0.7x1016.90 0.7x2.814.50 0.7x0.711.00 medium0.7x1004.1311.302.26 0.7x0.78.78 thinnest0.7x100 2.70 0.7x0.7 2.81 Inconsistency: uncertainty in loss tangent, mass and potential barrier of the carriers at oxide interface. obtained from Kleinpenning et. al, IEEE Trans. on Elec. Dev., vol. 42, 1995. as high as 1.8V and as high 1 V found in literature. unique for each sample.

43. UTA Noise and Reliability Laboratory 43 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

44. UTA Noise and Reliability Laboratory 44 Experimental and Simulated data Noise data measured at TI Simulation results vs. Measured Experimental data Simulated with existing model Simulated with modified model

45. UTA Noise and Reliability Laboratory 45 Computer source code Existing BERKELEY SPICE source code has been modified. Source code written at Texas Instruments Inc. by Douglas Weiser. and have been added to the existing noise model in addition to. An area scaling factor has been added to the equations to make the noise models scalable. The modified BERKELEY SPICE source code is available to the SRC (Semiconductor Research Corporation) member companies (TI, Intel, IBM, Motorola, National Semiconductor Corporation, AMD, etc.)

46. UTA Noise and Reliability Laboratory 46 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

47. UTA Noise and Reliability Laboratory 47 xyz shallow trench n+ poly Si emitter SiGe epi-SiGe poly interface dielectric isolation n+ Si emitter p+ SiGe poly DTI (deep trench isolation) p+ SiGe epi p+ SiGe epi DTI (deep Trench isolation) p SiGe epi DTI (deep trench isolation) Device structure under investigation x = emitter-poly overlap y = composite enclosure of poly z = DTI enclosure of composite Selectively implanted collector Transistors described as x-y-z; e.g. SIC:25-10-25.

48. UTA Noise and Reliability Laboratory 48 Dominant noise source Calculated S VC /S VB with S IB contribution dominant closely matches experimental S VC /S VB ; S IB contribution dominant. I B increases r π decreases coherence increases.

49. UTA Noise and Reliability Laboratory 49 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

50. UTA Noise and Reliability Laboratory 50 Selectively implanted collector (SIC) Higher collector doping Higher collector- base capacitance Lower Retarded Kirk- effect Higher Selectively implanted collector Higher and reduced degradation of Reduced base-width by compensation of boron tail

51. UTA Noise and Reliability Laboratory 51 Effect of selectively implanted collector SIC retards Kirk-effecthigher β for wider range of bias. No degradation in noise.

52. UTA Noise and Reliability Laboratory 52 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

53. UTA Noise and Reliability Laboratory 53 Higher extrinsic base implant (HEBI) High dose implantation in extrinsic base Smaller base resistance Higher Lower RF noise figure

54. UTA Noise and Reliability Laboratory 54 Effect of higher extrinsic base implant Higher gain for higher extrinsic base implant is possibly due to relative changes in Ge profile. No degradation in noise.

55. UTA Noise and Reliability Laboratory 55 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

56. UTA Noise and Reliability Laboratory 56 SiGe epi-SiGe poly interface Non-selective epitaxial growth of SiGe base SiGe epi on top of exposed Si SiGe poly on top of shallow trench Interface of epitaxial and polycrystalline SiGe smaller distance between SiGe epi-SiGe poly interface & intrinsic base Smaller base- collector capacitance Higher

57. UTA Noise and Reliability Laboratory 57 Effect of SiGe epi-SiGe poly interface No significant impact on DC characteristics. No degradation in noise; boron implantation in extrinsic base passivates the interface-defects.

58. UTA Noise and Reliability Laboratory 58 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

59. UTA Noise and Reliability Laboratory 59 Effect of emitter-poly overlap Significant g-r noise for smaller emitter-poly overlap. g-r noise diminished at higher currents in comparison to increased 1/f noise.

60. UTA Noise and Reliability Laboratory 60 Effect of emitter-poly overlap (cont.) Higher non-ideal base current for smaller emitter-poly overlap. S IB deviates from ~I B 2 dependence for smaller emitter-poly overlap.

61. UTA Noise and Reliability Laboratory 61 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

62. UTA Noise and Reliability Laboratory 62 Physical origin of S IB All except smaller emitter-poly overlap η r ≤1.6, AF≈2. Smaller emitter-poly overlap η r >3, AF≈1.

63. UTA Noise and Reliability Laboratory 63 S IB model Total number of traps in emitter- base junction. Characteristics time constant of i th trap. SRH g-r centers in E-B depletion region Capture and emission of carriers Perturbation in free carrier density Continuous distribution of time constants 1/f noise Superposition of Lorentzians ::

64. UTA Noise and Reliability Laboratory 64 Noise from Surface recombination current Smaller emitter- poly overlap Extrinsic base moves closer to emitter perimeter Two parallel BJTs n+ emitter, p SiGe intrinsic base, collector n+ emitter, p+ SiGe extrinsic base, collector Thin depletion region & high electric field Recombination through trap assisted tunneling n+ emitter - p+ extrinsic base diode n+ poly Si emitter p SiGe epi (intrinsic base) p+ SiGe epi (extrinsic base) n+ Si emitter dielectric isolation

65. UTA Noise and Reliability Laboratory 65 S IB model for smaller emitter-poly overlap Oxide slow state volume density. Attenuation tunneling distance. Area of surface region. Surface capacitance per unit area. : : : : From intrinsic E-B junction From surface of E-B junction

66. UTA Noise and Reliability Laboratory 66 I B (A) V BE (V) = 9.65x10 15 ~ 3.08x10 16 /eV/cm 3. Published values = 10 17 ~ 10 18 /ev/cm 3. Uncertainties in and. Separation of S IB components

67. UTA Noise and Reliability Laboratory 67 Outline Introduction: Limitations in existing noise models. Importance and motivation of research. Noise in polysilicon emitter bipolar transistors: Experimental setup. S IB modeling: noise mechanisms, effect of bias, geometry and IFO. S IC modeling: noise mechanisms, effect of bias and IFO. S Vr modeling: Collector-emitter measurement setup, effect of bias and IFO. Computer codes. Noise in SiGe heterojunction bipolar transistors: Dominant noise source. Effect of selective collector implant. Effect of higher extrinsic base implant. Effect of SiGe epi-SiGe poly interface. Effect of emitter-poly overlap. Physical origin and modeling of S IB. Conclusion

68. UTA Noise and Reliability Laboratory 68 Conclusion The base current fluctuations dominate at relatively high external base resistance values. Collector current fluctuations contribute when the external base resistance becomes comparable to or less than the input resistance. Fluctuations caused by the internal emitter resistance take over for high currents with small base resistance. From the dependence of noise magnitude on the geometry and temperature, fluctuations in the non-ideal base current was neglected. Polysilicon emitter bipolar transistors:

69. UTA Noise and Reliability Laboratory 69 Conclusion (cont.) S IB originates from diffusion fluctuations of minority carriers in poly and monosilicon emitter, and tunneling fluctuations of minority carriers at IFO; S IC from diffusion and number fluctuations of minority carriers in base, and S Vre from tunneling fluctuations of majority carrier at IFO. Diffusion fluctuations dominate over the tunneling fluctuations for larger devices; tunneling fluctuations dominate over diffusion fluctuations for the smaller ones. IFO increases the current gain significantly in NPN; both tunneling and diffusion fluctuations contribute. No significant improvement with increasing IFO thickness in PNP; diffusion fluctuations dominant.

70. UTA Noise and Reliability Laboratory 70 Conclusion (cont.) Selectively implanted collector causes higher current gain for wider range of bias; no noise degradation. No significant effect of SiGe epi-SiGe poly interface and higher extrinsic base implant. Severe impact of smaller emitter-poly overlap: increases non-ideality of the base current; trap assisted tunneling current due to parasitic BJT. g-r noise at lower bias currents. At higher bias currents, fluctuations from trap assisted tunneling current contribute. For all transistors except smaller emitter poly overlap, noise originates from intrinsic E-B junction. SiGe heterojunction bipolar transistors:

71. UTA Noise and Reliability Laboratory 71 Acknowledgements Zeynep Celik-Butler Supervising Professor: UTA Noise & Microsensor Group: Semiconductor Research Corporation: Texas Higher Education Board, Advanced Technology Prog. Texas Instruments Inc. National Semiconductor Corporation Bigang Min, Siva P. Devireddy, Shadi Dayeh, Enhai Zhao